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removing some arduino libraries

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mitchellhansen 5 years ago
parent d82460ee37
commit 72cea94613
2442 changed files with 1 additions and 853896 deletions
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2
CMakeLists.txt
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@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 2.6)
set(MCU "atmega328p" )
set(CPU_SPEED "16000000" )
set(PORT "/dev/ttyUSB1")
set(PORT "/dev/ttyUSB0")
set(PORT_SPEED "57600")
set(PIN_VARIANT "standard")
set(ARDUINO_PATH "arduino")

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59
arduino/hardware/tools/avr/avr/include/alloca.h
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@ -1,59 +0,0 @@
/* Copyright (c) 2007, Dmitry Xmelkov
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _ALLOCA_H
#define _ALLOCA_H 1
#include <stddef.h>
/** \defgroup alloca <alloca.h>: Allocate space in the stack */
/** \ingroup alloca
\brief Allocate \a __size bytes of space in the stack frame of the caller.
This temporary space is automatically freed when the function that
called alloca() returns to its caller. Avr-libc defines the alloca() as
a macro, which is translated into the inlined \c __builtin_alloca()
function. The fact that the code is inlined, means that it is impossible
to take the address of this function, or to change its behaviour by
linking with a different library.
\return alloca() returns a pointer to the beginning of the allocated
space. If the allocation causes stack overflow, program behaviour is
undefined.
\warning Avoid use alloca() inside the list of arguments of a function
call.
*/
extern void *alloca (size_t __size);
#define alloca(size) __builtin_alloca (size)
#endif /* alloca.h */

120
arduino/hardware/tools/avr/avr/include/assert.h
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@ -1,120 +0,0 @@
/* Copyright (c) 2005,2007 Joerg Wunsch
All rights reserved.
Portions of documentation Copyright (c) 1991, 1993
The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
$Id$
*/
/** \file */
/** \defgroup avr_assert <assert.h>: Diagnostics
\code #include <assert.h> \endcode
This header file defines a debugging aid.
As there is no standard error output stream available for many
applications using this library, the generation of a printable
error message is not enabled by default. These messages will
only be generated if the application defines the macro
\code __ASSERT_USE_STDERR \endcode
before including the \c <assert.h> header file. By default,
only abort() will be called to halt the application.
*/
/*@{*/
/*
* The ability to include this file (with or without NDEBUG) is a
* feature.
*/
#undef assert
#include <stdlib.h>
#if defined(__DOXYGEN__)
/**
* \def assert
* \param expression Expression to test for.
*
* The assert() macro tests the given expression and if it is false,
* the calling process is terminated. A diagnostic message is written
* to stderr and the function abort() is called, effectively
* terminating the program.
*
* If expression is true, the assert() macro does nothing.
*
* The assert() macro may be removed at compile time by defining
* NDEBUG as a macro (e.g., by using the compiler option -DNDEBUG).
*/
# define assert(expression)
#else /* !DOXYGEN */
# if defined(NDEBUG)
# define assert(e) ((void)0)
# else /* !NDEBUG */
# if defined(__ASSERT_USE_STDERR)
# define assert(e) ((e) ? (void)0 : \
__assert(__func__, __FILE__, __LINE__, #e))
# else /* !__ASSERT_USE_STDERR */
# define assert(e) ((e) ? (void)0 : abort())
# endif /* __ASSERT_USE_STDERR */
# endif /* NDEBUG */
#endif /* DOXYGEN */
#if (defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) || \
((_GNUC_ > 4 || (_GNUC_ == 4 && _GNUC_MINOR_ >= 6)) && !defined __cplusplus)
# undef static_assert
# define static_assert _Static_assert
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(__DOXYGEN__)
extern void __assert(const char *__func, const char *__file,
int __lineno, const char *__sexp);
#endif /* not __DOXYGEN__ */
#ifdef __cplusplus
}
#endif
/*@}*/
/* EOF */

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arduino/hardware/tools/avr/avr/include/avr/boot.h
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/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_BOOT_H_
#define _AVR_BOOT_H_ 1
/** \file */
/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
\code
#include <avr/io.h>
#include <avr/boot.h>
\endcode
The macros in this module provide a C language interface to the
bootloader support functionality of certain AVR processors. These
macros are designed to work with all sizes of flash memory.
Global interrupts are not automatically disabled for these macros. It
is left up to the programmer to do this. See the code example below.
Also see the processor datasheet for caveats on having global interrupts
enabled during writing of the Flash.
\note Not all AVR processors provide bootloader support. See your
processor datasheet to see if it provides bootloader support.
\todo From email with Marek: On smaller devices (all except ATmega64/128),
__SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
instructions - since the boot loader has a limited size, this could be an
important optimization.
\par API Usage Example
The following code shows typical usage of the boot API.
\code
#include <inttypes.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
void boot_program_page (uint32_t page, uint8_t *buf)
{
uint16_t i;
uint8_t sreg;
// Disable interrupts.
sreg = SREG;
cli();
eeprom_busy_wait ();
boot_page_erase (page);
boot_spm_busy_wait (); // Wait until the memory is erased.
for (i=0; i<SPM_PAGESIZE; i+=2)
{
// Set up little-endian word.
uint16_t w = *buf++;
w += (*buf++) << 8;
boot_page_fill (page + i, w);
}
boot_page_write (page); // Store buffer in flash page.
boot_spm_busy_wait(); // Wait until the memory is written.
// Reenable RWW-section again. We need this if we want to jump back
// to the application after bootloading.
boot_rww_enable ();
// Re-enable interrupts (if they were ever enabled).
SREG = sreg;
}\endcode */
#include <avr/eeprom.h>
#include <avr/io.h>
#include <inttypes.h>
#include <limits.h>
/* Check for SPM Control Register in processor. */
#if defined (SPMCSR)
# define __SPM_REG SPMCSR
#else
# if defined (SPMCR)
# define __SPM_REG SPMCR
# else
# error AVR processor does not provide bootloader support!
# endif
#endif
/* Check for SPM Enable bit. */
#if defined(SPMEN)
# define __SPM_ENABLE SPMEN
#elif defined(SELFPRGEN)
# define __SPM_ENABLE SELFPRGEN
#else
# error Cannot find SPM Enable bit definition!
#endif
/** \ingroup avr_boot
\def BOOTLOADER_SECTION
Used to declare a function or variable to be placed into a
new section called .bootloader. This section and its contents
can then be relocated to any address (such as the bootloader
NRWW area) at link-time. */
#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
#ifndef __DOXYGEN__
/* Create common bit definitions. */
#ifdef ASB
#define __COMMON_ASB ASB
#else
#define __COMMON_ASB RWWSB
#endif
#ifdef ASRE
#define __COMMON_ASRE ASRE
#else
#define __COMMON_ASRE RWWSRE
#endif
/* Define the bit positions of the Boot Lock Bits. */
#define BLB12 5
#define BLB11 4
#define BLB02 3
#define BLB01 2
#endif /* __DOXYGEN__ */
/** \ingroup avr_boot
\def boot_spm_interrupt_enable()
Enable the SPM interrupt. */
#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
/** \ingroup avr_boot
\def boot_spm_interrupt_disable()
Disable the SPM interrupt. */
#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
/** \ingroup avr_boot
\def boot_is_spm_interrupt()
Check if the SPM interrupt is enabled. */
#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
/** \ingroup avr_boot
\def boot_rww_busy()
Check if the RWW section is busy. */
#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
/** \ingroup avr_boot
\def boot_spm_busy()
Check if the SPM instruction is busy. */
#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
/** \ingroup avr_boot
\def boot_spm_busy_wait()
Wait while the SPM instruction is busy. */
#define boot_spm_busy_wait() do{}while(boot_spm_busy())
#ifndef __DOXYGEN__
#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
#if defined(BLBSET)
#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */
#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB))
#endif
#define __boot_page_fill_normal(address, data) \
(__extension__({ \
__asm__ __volatile__ \
( \
"movw r0, %3\n\t" \
"sts %0, %1\n\t" \
"spm\n\t" \
"clr r1\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_FILL)), \
"z" ((uint16_t)(address)), \
"r" ((uint16_t)(data)) \
: "r0" \
); \
}))
#define __boot_page_fill_alternate(address, data)\
(__extension__({ \
__asm__ __volatile__ \
( \
"movw r0, %3\n\t" \
"sts %0, %1\n\t" \
"spm\n\t" \
".word 0xffff\n\t" \
"nop\n\t" \
"clr r1\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_FILL)), \
"z" ((uint16_t)(address)), \
"r" ((uint16_t)(data)) \
: "r0" \
); \
}))
#define __boot_page_fill_extended(address, data) \
(__extension__({ \
__asm__ __volatile__ \
( \
"movw r0, %4\n\t" \
"movw r30, %A3\n\t" \
"sts %1, %C3\n\t" \
"sts %0, %2\n\t" \
"spm\n\t" \
"clr r1\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
"r" ((uint8_t)(__BOOT_PAGE_FILL)), \
"r" ((uint32_t)(address)), \
"r" ((uint16_t)(data)) \
: "r0", "r30", "r31" \
); \
}))
#define __boot_page_erase_normal(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
"z" ((uint16_t)(address)) \
); \
}))
#define __boot_page_erase_alternate(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
".word 0xffff\n\t" \
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
"z" ((uint16_t)(address)) \
); \
}))
#define __boot_page_erase_extended(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"movw r30, %A3\n\t" \
"sts %1, %C3\n\t" \
"sts %0, %2\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
"r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
"r" ((uint32_t)(address)) \
: "r30", "r31" \
); \
}))
#define __boot_page_write_normal(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
"z" ((uint16_t)(address)) \
); \
}))
#define __boot_page_write_alternate(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
".word 0xffff\n\t" \
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
"z" ((uint16_t)(address)) \
); \
}))
#define __boot_page_write_extended(address) \
(__extension__({ \
__asm__ __volatile__ \
( \
"movw r30, %A3\n\t" \
"sts %1, %C3\n\t" \
"sts %0, %2\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
"r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
"r" ((uint32_t)(address)) \
: "r30", "r31" \
); \
}))
#define __boot_rww_enable() \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
); \
}))
#define __boot_rww_enable_alternate() \
(__extension__({ \
__asm__ __volatile__ \
( \
"sts %0, %1\n\t" \
"spm\n\t" \
".word 0xffff\n\t" \
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
); \
}))
/* From the mega16/mega128 data sheets (maybe others):
Bits by SPM To set the Boot Loader Lock bits, write the desired data to
R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
that may prevent the Application and Boot Loader section from any
software update by the MCU.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
will be programmed if an SPM instruction is executed within four cycles
after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
don't care during this operation, but for future compatibility it is
recommended to load the Z-pointer with $0001 (same as used for reading the
Lock bits). For future compatibility It is also recommended to set bits 7,
6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
Lock bits the entire Flash can be read during the operation. */
#define __boot_lock_bits_set(lock_bits) \
(__extension__({ \
uint8_t value = (uint8_t)(~(lock_bits)); \
__asm__ __volatile__ \
( \
"ldi r30, 1\n\t" \
"ldi r31, 0\n\t" \
"mov r0, %2\n\t" \
"sts %0, %1\n\t" \
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
"r" (value) \
: "r0", "r30", "r31" \
); \
}))
#define __boot_lock_bits_set_alternate(lock_bits) \
(__extension__({ \
uint8_t value = (uint8_t)(~(lock_bits)); \
__asm__ __volatile__ \
( \
"ldi r30, 1\n\t" \
"ldi r31, 0\n\t" \
"mov r0, %2\n\t" \
"sts %0, %1\n\t" \
"spm\n\t" \
".word 0xffff\n\t" \
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
"r" (value) \
: "r0", "r30", "r31" \
); \
}))
#endif /* __DOXYGEN__ */
/*
Reading lock and fuse bits:
Similarly to writing the lock bits above, set BLBSET and SPMEN (or
SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
LPM instruction.
Z address: contents:
0x0000 low fuse bits
0x0001 lock bits
0x0002 extended fuse bits
0x0003 high fuse bits
Sounds confusing, doesn't it?
Unlike the macros in pgmspace.h, no need to care for non-enhanced
cores here as these old cores do not provide SPM support anyway.
*/
/** \ingroup avr_boot
\def GET_LOW_FUSE_BITS
address to read the low fuse bits, using boot_lock_fuse_bits_get
*/
#define GET_LOW_FUSE_BITS (0x0000)
/** \ingroup avr_boot
\def GET_LOCK_BITS
address to read the lock bits, using boot_lock_fuse_bits_get
*/
#define GET_LOCK_BITS (0x0001)
/** \ingroup avr_boot
\def GET_EXTENDED_FUSE_BITS
address to read the extended fuse bits, using boot_lock_fuse_bits_get
*/
#define GET_EXTENDED_FUSE_BITS (0x0002)
/** \ingroup avr_boot
\def GET_HIGH_FUSE_BITS
address to read the high fuse bits, using boot_lock_fuse_bits_get
*/
#define GET_HIGH_FUSE_BITS (0x0003)
/** \ingroup avr_boot
\def boot_lock_fuse_bits_get(address)
Read the lock or fuse bits at \c address.
Parameter \c address can be any of GET_LOW_FUSE_BITS,
GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
\note The lock and fuse bits returned are the physical values,
i.e. a bit returned as 0 means the corresponding fuse or lock bit
is programmed.
*/
#define boot_lock_fuse_bits_get(address) \
(__extension__({ \
uint8_t __result; \
__asm__ __volatile__ \
( \
"sts %1, %2\n\t" \
"lpm %0, Z\n\t" \
: "=r" (__result) \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
"z" ((uint16_t)(address)) \
); \
__result; \
}))
#ifndef __DOXYGEN__
#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
#endif
/** \ingroup avr_boot
\def boot_signature_byte_get(address)
Read the Signature Row byte at \c address. For some MCU types,
this function can also retrieve the factory-stored oscillator
calibration bytes.
Parameter \c address can be 0-0x1f as documented by the datasheet.
\note The values are MCU type dependent.
*/
#define boot_signature_byte_get(addr) \
(__extension__({ \
uint8_t __result; \
__asm__ __volatile__ \
( \
"sts %1, %2\n\t" \
"lpm %0, Z" "\n\t" \
: "=r" (__result) \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"r" ((uint8_t)(__BOOT_SIGROW_READ)), \
"z" ((uint16_t)(addr)) \
); \
__result; \
}))
/** \ingroup avr_boot
\def boot_page_fill(address, data)
Fill the bootloader temporary page buffer for flash
address with data word.
\note The address is a byte address. The data is a word. The AVR
writes data to the buffer a word at a time, but addresses the buffer
per byte! So, increment your address by 2 between calls, and send 2
data bytes in a word format! The LSB of the data is written to the lower
address; the MSB of the data is written to the higher address.*/
/** \ingroup avr_boot
\def boot_page_erase(address)
Erase the flash page that contains address.
\note address is a byte address in flash, not a word address. */
/** \ingroup avr_boot
\def boot_page_write(address)
Write the bootloader temporary page buffer
to flash page that contains address.
\note address is a byte address in flash, not a word address. */
/** \ingroup avr_boot
\def boot_rww_enable()
Enable the Read-While-Write memory section. */
/** \ingroup avr_boot
\def boot_lock_bits_set(lock_bits)
Set the bootloader lock bits.
\param lock_bits A mask of which Boot Loader Lock Bits to set.
\note In this context, a 'set bit' will be written to a zero value.
Note also that only BLBxx bits can be programmed by this command.
For example, to disallow the SPM instruction from writing to the Boot
Loader memory section of flash, you would use this macro as such:
\code
boot_lock_bits_set (_BV (BLB11));
\endcode
\note Like any lock bits, the Boot Loader Lock Bits, once set,
cannot be cleared again except by a chip erase which will in turn
also erase the boot loader itself. */
/* Normal versions of the macros use 16-bit addresses.
Extended versions of the macros use 32-bit addresses.
Alternate versions of the macros use 16-bit addresses and require special
instruction sequences after LPM.
FLASHEND is defined in the ioXXXX.h file.
USHRT_MAX is defined in <limits.h>. */
#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
|| defined(__AVR_ATmega323__)
/* Alternate: ATmega161/163/323 and 16 bit address */
#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
#define boot_page_erase(address) __boot_page_erase_alternate(address)
#define boot_page_write(address) __boot_page_write_alternate(address)
#define boot_rww_enable() __boot_rww_enable_alternate()
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
#elif (FLASHEND > USHRT_MAX)
/* Extended: >16 bit address */
#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
#define boot_page_erase(address) __boot_page_erase_extended(address)
#define boot_page_write(address) __boot_page_write_extended(address)
#define boot_rww_enable() __boot_rww_enable()
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
#else
/* Normal: 16 bit address */
#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
#define boot_page_erase(address) __boot_page_erase_normal(address)
#define boot_page_write(address) __boot_page_write_normal(address)
#define boot_rww_enable() __boot_rww_enable()
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
#endif
/** \ingroup avr_boot
Same as boot_page_fill() except it waits for eeprom and spm operations to
complete before filling the page. */
#define boot_page_fill_safe(address, data) \
do { \
boot_spm_busy_wait(); \
eeprom_busy_wait(); \
boot_page_fill(address, data); \
} while (0)
/** \ingroup avr_boot
Same as boot_page_erase() except it waits for eeprom and spm operations to
complete before erasing the page. */
#define boot_page_erase_safe(address) \
do { \
boot_spm_busy_wait(); \
eeprom_busy_wait(); \
boot_page_erase (address); \
} while (0)
/** \ingroup avr_boot
Same as boot_page_write() except it waits for eeprom and spm operations to
complete before writing the page. */
#define boot_page_write_safe(address) \
do { \
boot_spm_busy_wait(); \
eeprom_busy_wait(); \
boot_page_write (address); \
} while (0)
/** \ingroup avr_boot
Same as boot_rww_enable() except waits for eeprom and spm operations to
complete before enabling the RWW mameory. */
#define boot_rww_enable_safe() \
do { \
boot_spm_busy_wait(); \
eeprom_busy_wait(); \
boot_rww_enable(); \
} while (0)
/** \ingroup avr_boot
Same as boot_lock_bits_set() except waits for eeprom and spm operations to
complete before setting the lock bits. */
#define boot_lock_bits_set_safe(lock_bits) \
do { \
boot_spm_busy_wait(); \
eeprom_busy_wait(); \
boot_lock_bits_set (lock_bits); \
} while (0)
#endif /* _AVR_BOOT_H_ */

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/* Copyright (c) 2008 Anatoly Sokolov
Copyright (c) 2010 Joerg Wunsch
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
/*
avr/builtins.h - Intrinsic functions built into the compiler
*/
#ifndef _AVR_BUILTINS_H_
#define _AVR_BUILTINS_H_
#ifndef __HAS_DELAY_CYCLES
#define __HAS_DELAY_CYCLES 1
#endif
/** \file */
/** \defgroup avr_builtins <avr/builtins.h>: GCC builtins
\code #include <avr/builtins.h> \endcode
This header file declares AVR builtins.
All the functions documented here are built into the
compiler, and cause it to emit the corresponding assembly
code instructions.
*/
/**
\ingroup avr_builtins
Enables interrupts by setting the global interrupt mask. */
extern void __builtin_avr_sei(void);
/**
\ingroup avr_builtins
Disables all interrupts by clearing the global interrupt mask. */
extern void __builtin_avr_cli(void);
/**
\ingroup avr_builtins
Emits a \c SLEEP instruction. */
extern void __builtin_avr_sleep(void);
/**
\ingroup avr_builtins
Emits a WDR (watchdog reset) instruction. */
extern void __builtin_avr_wdr(void);
/**
\ingroup avr_builtins
Emits a SWAP (nibble swap) instruction on __b. */
extern unsigned char __builtin_avr_swap(unsigned char __b);
/**
\ingroup avr_builtins
Emits an FMUL (fractional multiply unsigned) instruction. */
extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b);
/**
\ingroup avr_builtins
Emits an FMUL (fractional multiply signed) instruction. */
extern int __builtin_avr_fmuls(char __a, char __b);
/**
\ingroup avr_builtins
Emits an FMUL (fractional multiply signed with unsigned) instruction. */
extern int __builtin_avr_fmulsu(char __a, unsigned char __b);
#if __HAS_DELAY_CYCLES || defined(__DOXYGEN__)
/**
\ingroup avr_builtins
Emits a sequence of instructions causing the CPU to spend
\c __n cycles on it. */
extern void __builtin_avr_delay_cycles(unsigned long __n);
#endif
#endif /* _AVR_BUILTINS_H_ */

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/* Copyright (c) 2007 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_COMMON_H
#define _AVR_COMMON_H
#include <avr/sfr_defs.h>
/*
This purpose of this header is to define registers that have not been
previously defined in the individual device IO header files, and to define
other symbols that are common across AVR device families.
This file is designed to be included in <avr/io.h> after the individual
device IO header files, and after <avr/sfr_defs.h>
*/
/*------------ Registers Not Previously Defined ------------*/
/*
These are registers that are not previously defined in the individual
IO header files, OR they are defined here because they are used in parts of
avr-libc even if a device is not selected but a general architecture has
been selected.
*/
/*
Stack pointer register.
AVR architecture 1 has no RAM, thus no stack pointer.
All other architectures do have a stack pointer. Some devices have only
less than 256 bytes of possible RAM locations (128 Bytes of SRAM
and no option for external RAM), thus SPH is officially "reserved"
for them.
*/
#if __AVR_ARCH__ >= 100
# ifndef SPL
# define SPL _SFR_MEM8(0x3D)
# endif
# ifndef SPH
# define SPH _SFR_MEM8(0x3E)
# endif
# ifndef SP
# define SP _SFR_MEM16(0x3D)
# endif
#elif __AVR_ARCH__ != 1
# ifndef SPL
# define SPL _SFR_IO8(0x3D)
# endif
# if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__)
# ifndef SP
# define SP _SFR_IO8(0x3D)
# endif
# else
# ifndef SP
# define SP _SFR_IO16(0x3D)
# endif
# ifndef SPH
# define SPH _SFR_IO8(0x3E)
# endif
# endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */
#endif /* __AVR_ARCH__ != 1 */
/* Status Register */
#ifndef SREG
# if __AVR_ARCH__ >= 100
# define SREG _SFR_MEM8(0x3F)
# else
# define SREG _SFR_IO8(0x3F)
# endif
#endif
/* SREG bit definitions */
#ifndef SREG_C
# define SREG_C (0)
#endif
#ifndef SREG_Z
# define SREG_Z (1)
#endif
#ifndef SREG_N
# define SREG_N (2)
#endif
#ifndef SREG_V
# define SREG_V (3)
#endif
#ifndef SREG_S
# define SREG_S (4)
#endif
#ifndef SREG_H
# define SREG_H (5)
#endif
#ifndef SREG_T
# define SREG_T (6)
#endif
#ifndef SREG_I
# define SREG_I (7)
#endif
#if defined(__COMPILING_AVR_LIBC__)
/* AVR 6 Architecture */
# if __AVR_ARCH__ == 6
# ifndef EIND
# define EIND _SFR_IO8(0X3C)
# endif
/* XMEGA Architectures */
# elif __AVR_ARCH__ >= 100
# ifndef EIND
# define EIND _SFR_MEM8(0x3C)
# endif
# endif
/*
Only few devices come without EEPROM. In order to assemble the
EEPROM library components without defining a specific device, we
keep the EEPROM-related definitions here.
*/
/* EEPROM Control Register */
# ifndef EECR
# define EECR _SFR_IO8(0x1C)
# endif
/* EEPROM Data Register */
# ifndef EEDR
# define EEDR _SFR_IO8(0x1D)
# endif
/* EEPROM Address Register */
# ifndef EEAR
# define EEAR _SFR_IO16(0x1E)
# endif
# ifndef EEARL
# define EEARL _SFR_IO8(0x1E)
# endif
# ifndef EEARH
# define EEARH _SFR_IO8(0x1F)
# endif
/* EEPROM Control Register bits */
# ifndef EERE
# define EERE (0)
# endif
# ifndef EEWE
# define EEWE (1)
# endif
# ifndef EEMWE
# define EEMWE (2)
# endif
# ifndef EERIE
# define EERIE (3)
# endif
/* RAM Page Z Select Register */
#ifndef RAMPZ
# if defined(__AVR_HAVE_RAMPZ__) && __AVR_HAVE_RAMPZ__
# if __AVR_ARCH__ >= 100
# define RAMPZ _SFR_MEM8(0x3B)
# else
# define RAMPZ _SFR_IO8(0x3B)
# endif
# endif
#endif
#endif /* __COMPILING_AVR_LIBC__ */
/*------------ Common Symbols ------------*/
/*
Generic definitions for registers that are common across multiple AVR devices
and families.
*/
/* Pointer registers definitions */
#if __AVR_ARCH__ != 1 /* avr1 does not have X and Y pointers */
# define XL r26
# define XH r27
# define YL r28
# define YH r29
#endif /* #if __AVR_ARCH__ != 1 */
#define ZL r30
#define ZH r31
/* Status Register */
#if defined(SREG)
# define AVR_STATUS_REG SREG
# if __AVR_ARCH__ >= 100
# define AVR_STATUS_ADDR _SFR_MEM_ADDR(SREG)
# else
# define AVR_STATUS_ADDR _SFR_IO_ADDR(SREG)
# endif
#endif
/* Stack Pointer (combined) Register */
#if defined(SP)
# define AVR_STACK_POINTER_REG SP
# if __AVR_ARCH__ >= 100
# define AVR_STACK_POINTER_ADDR _SFR_MEM_ADDR(SP)
# else
# define AVR_STACK_POINTER_ADDR _SFR_IO_ADDR(SP)
# endif
#endif
/* Stack Pointer High Register */
#if defined(SPH)
# define _HAVE_AVR_STACK_POINTER_HI 1
# define AVR_STACK_POINTER_HI_REG SPH
# if __AVR_ARCH__ >= 100
# define AVR_STACK_POINTER_HI_ADDR _SFR_MEM_ADDR(SPH)
# else
# define AVR_STACK_POINTER_HI_ADDR _SFR_IO_ADDR(SPH)
# endif
#endif
/* Stack Pointer Low Register */
#if defined(SPL)
# define AVR_STACK_POINTER_LO_REG SPL
# if __AVR_ARCH__ >= 100
# define AVR_STACK_POINTER_LO_ADDR _SFR_MEM_ADDR(SPL)
# else
# define AVR_STACK_POINTER_LO_ADDR _SFR_IO_ADDR(SPL)
# endif
#endif
/* RAMPD Register */
#if defined(RAMPD)
# define AVR_RAMPD_REG RAMPD
# if __AVR_ARCH__ >= 100
# define AVR_RAMPD_ADDR _SFR_MEM_ADDR(RAMPD)
# else
# define AVR_RAMPD_ADDR _SFR_IO_ADDR(RAMPD)
# endif
#endif
/* RAMPX Register */
#if defined(RAMPX)
# define AVR_RAMPX_REG RAMPX
# if __AVR_ARCH__ >= 100
# define AVR_RAMPX_ADDR _SFR_MEM_ADDR(RAMPX)
# else
# define AVR_RAMPX_ADDR _SFR_IO_ADDR(RAMPX)
# endif
#endif
/* RAMPY Register */
#if defined(RAMPY)
# define AVR_RAMPY_REG RAMPY
# if __AVR_ARCH__ >= 100
# define AVR_RAMPY_ADDR _SFR_MEM_ADDR(RAMPY)
# else
# define AVR_RAMPY_ADDR _SFR_IO_ADDR(RAMPY)
# endif
#endif
/* RAMPZ Register */
#if defined(RAMPZ)
# define AVR_RAMPZ_REG RAMPZ
# if __AVR_ARCH__ >= 100
# define AVR_RAMPZ_ADDR _SFR_MEM_ADDR(RAMPZ)
# else
# define AVR_RAMPZ_ADDR _SFR_IO_ADDR(RAMPZ)
# endif
#endif
/* Extended Indirect Register */
#if defined(EIND)
# define AVR_EXTENDED_INDIRECT_REG EIND
# if __AVR_ARCH__ >= 100
# define AVR_EXTENDED_INDIRECT_ADDR _SFR_MEM_ADDR(EIND)
# else
# define AVR_EXTENDED_INDIRECT_ADDR _SFR_IO_ADDR(EIND)
# endif
#endif
/*------------ Workaround to old compilers (4.1.2 and earlier) ------------*/
#ifndef __AVR_HAVE_MOVW__
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
# define __AVR_HAVE_MOVW__ 1
# endif
#endif
#ifndef __AVR_HAVE_LPMX__
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
# define __AVR_HAVE_LPMX__ 1
# endif
#endif
#ifndef __AVR_HAVE_MUL__
# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
# define __AVR_HAVE_MUL__ 1
# endif
#endif
#endif /* _AVR_COMMON_H */

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/* Copyright (c) 2010, Joerg Wunsch
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
/* avr/cpufunc.h - Special CPU functions */
#ifndef _AVR_CPUFUNC_H_
#define _AVR_CPUFUNC_H_ 1
#include <stdint.h>
/** \file */
/** \defgroup avr_cpufunc <avr/cpufunc.h>: Special AVR CPU functions
\code #include <avr/cpufunc.h> \endcode
This header file contains macros that access special functions of
the AVR CPU which do not fit into any of the other header files.
*/
#if defined(__DOXYGEN__)
/**
\ingroup avr_cpufunc
\def _NOP
Execute a <i>no operation</i> (NOP) CPU instruction. This
should not be used to implement delays, better use the functions
from <util/delay_basic.h> or <util/delay.h> for this. For
debugging purposes, a NOP can be useful to have an instruction that
is guaranteed to be not optimized away by the compiler, so it can
always become a breakpoint in the debugger.
*/
#define _NOP()
#else /* real code */
#define _NOP() __asm__ __volatile__("nop")
#endif /* __DOXYGEN__ */
#if defined(__DOXYGEN__)
/**
\ingroup avr_cpufunc
\def _MemoryBarrier
Implement a read/write <i>memory barrier</i>. A memory
barrier instructs the compiler to not cache any memory data in
registers beyond the barrier. This can sometimes be more effective
than blocking certain optimizations by declaring some object with a
\c volatile qualifier.
See \ref optim_code_reorder for things to be taken into account
with respect to compiler optimizations.
*/
#define _MemoryBarrier()
#else /* real code */
#define _MemoryBarrier() __asm__ __volatile__("":::"memory")
#endif /* __DOXYGEN__ */
/**
\ingroup avr_cpufunc
Write \a __value to Configuration Change Protected (CCP) IO register
at \a __ioaddr.
*/
void ccp_write_io (uint8_t *__ioaddr, uint8_t __value);
#endif /* _AVR_CPUFUNC_H_ */

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arduino/hardware/tools/avr/avr/include/avr/crc16.h
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/* Copyright (c) 2005 Joerg Wunsch
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_CRC16_H_
#define _AVR_CRC16_H_
#warning "This file has been moved to <util/crc16.h>."
#include <util/crc16.h>
#endif /* _AVR_CRC16_H_ */

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arduino/hardware/tools/avr/avr/include/avr/delay.h
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/* Copyright (c) 2005 Joerg Wunsch
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_DELAY_H_
#define _AVR_DELAY_H_
#warning "This file has been moved to <util/delay.h>."
#include <util/delay.h>
#endif /* _AVR_DELAY_H_ */

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arduino/hardware/tools/avr/avr/include/avr/eeprom.h
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/* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
Copyright (c) 2005, 2006 Bjoern Haase
Copyright (c) 2008 Atmel Corporation
Copyright (c) 2008 Wouter van Gulik
Copyright (c) 2009 Dmitry Xmelkov
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_EEPROM_H_
#define _AVR_EEPROM_H_ 1
#include <avr/io.h>
#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__)
# warning "Device does not have EEPROM available."
#else
#if defined (EEAR) && !defined (EEARL) && !defined (EEARH)
#define EEARL EEAR
#endif
#ifndef __ASSEMBLER__
#include <stddef.h> /* size_t */
#include <stdint.h>
/** \defgroup avr_eeprom <avr/eeprom.h>: EEPROM handling
\code #include <avr/eeprom.h> \endcode
This header file declares the interface to some simple library
routines suitable for handling the data EEPROM contained in the
AVR microcontrollers. The implementation uses a simple polled
mode interface. Applications that require interrupt-controlled
EEPROM access to ensure that no time will be wasted in spinloops
will have to deploy their own implementation.
\par Notes:
- In addition to the write functions there is a set of update ones.
This functions read each byte first and skip the burning if the
old value is the same with new. The scaning direction is from
high address to low, to obtain quick return in common cases.
- All of the read/write functions first make sure the EEPROM is
ready to be accessed. Since this may cause long delays if a
write operation is still pending, time-critical applications
should first poll the EEPROM e. g. using eeprom_is_ready() before
attempting any actual I/O. But this functions are not wait until
SELFPRGEN in SPMCSR becomes zero. Do this manually, if your
softwate contains the Flash burning.
- As these functions modify IO registers, they are known to be
non-reentrant. If any of these functions are used from both,
standard and interrupt context, the applications must ensure
proper protection (e.g. by disabling interrupts before accessing
them).
- All write functions force erase_and_write programming mode.
- For Xmega the EEPROM start address is 0, like other architectures.
The reading functions add the 0x2000 value to use EEPROM mapping into
data space.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __ATTR_PURE__
# ifdef __DOXYGEN__
# define __ATTR_PURE__
# else
# define __ATTR_PURE__ __attribute__((__pure__))
# endif
#endif
/** \def EEMEM
\ingroup avr_eeprom
Attribute expression causing a variable to be allocated within the
.eeprom section. */
#define EEMEM __attribute__((section(".eeprom")))
/** \def eeprom_is_ready
\ingroup avr_eeprom
\returns 1 if EEPROM is ready for a new read/write operation, 0 if not.
*/
#if defined (__DOXYGEN__)
# define eeprom_is_ready()
#elif defined (__AVR_XMEGA__) && __AVR_XMEGA__
# define eeprom_is_ready() bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp)
#elif defined (DEECR)
# define eeprom_is_ready() bit_is_clear (DEECR, BSY)
#elif defined (EEPE)
# define eeprom_is_ready() bit_is_clear (EECR, EEPE)
#else
# define eeprom_is_ready() bit_is_clear (EECR, EEWE)
#endif
/** \def eeprom_busy_wait
\ingroup avr_eeprom
Loops until the eeprom is no longer busy.
\returns Nothing.
*/
#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
/** \ingroup avr_eeprom
Read one byte from EEPROM address \a __p.
*/
uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read one 16-bit word (little endian) from EEPROM address \a __p.
*/
uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read one 32-bit double word (little endian) from EEPROM address \a __p.
*/
uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read one float value (little endian) from EEPROM address \a __p.
*/
float eeprom_read_float (const float *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read a block of \a __n bytes from EEPROM address \a __src to SRAM
\a __dst.
*/
void eeprom_read_block (void *__dst, const void *__src, size_t __n);
/** \ingroup avr_eeprom
Write a byte \a __value to EEPROM address \a __p.
*/
void eeprom_write_byte (uint8_t *__p, uint8_t __value);
/** \ingroup avr_eeprom
Write a word \a __value to EEPROM address \a __p.
*/
void eeprom_write_word (uint16_t *__p, uint16_t __value);
/** \ingroup avr_eeprom
Write a 32-bit double word \a __value to EEPROM address \a __p.
*/
void eeprom_write_dword (uint32_t *__p, uint32_t __value);
/** \ingroup avr_eeprom
Write a float \a __value to EEPROM address \a __p.
*/
void eeprom_write_float (float *__p, float __value);
/** \ingroup avr_eeprom
Write a block of \a __n bytes to EEPROM address \a __dst from \a __src.
\note The argument order is mismatch with common functions like strcpy().
*/
void eeprom_write_block (const void *__src, void *__dst, size_t __n);
/** \ingroup avr_eeprom
Update a byte \a __value to EEPROM address \a __p.
*/
void eeprom_update_byte (uint8_t *__p, uint8_t __value);
/** \ingroup avr_eeprom
Update a word \a __value to EEPROM address \a __p.
*/
void eeprom_update_word (uint16_t *__p, uint16_t __value);
/** \ingroup avr_eeprom
Update a 32-bit double word \a __value to EEPROM address \a __p.
*/
void eeprom_update_dword (uint32_t *__p, uint32_t __value);
/** \ingroup avr_eeprom
Update a float \a __value to EEPROM address \a __p.
*/
void eeprom_update_float (float *__p, float __value);
/** \ingroup avr_eeprom
Update a block of \a __n bytes to EEPROM address \a __dst from \a __src.
\note The argument order is mismatch with common functions like strcpy().
*/
void eeprom_update_block (const void *__src, void *__dst, size_t __n);
/** \name IAR C compatibility defines */
/*@{*/
/** \def _EEPUT
\ingroup avr_eeprom
Write a byte to EEPROM. Compatibility define for IAR C. */
#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
/** \def __EEPUT
\ingroup avr_eeprom
Write a byte to EEPROM. Compatibility define for IAR C. */
#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
/** \def _EEGET
\ingroup avr_eeprom
Read a byte from EEPROM. Compatibility define for IAR C. */
#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
/** \def __EEGET
\ingroup avr_eeprom
Read a byte from EEPROM. Compatibility define for IAR C. */
#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
/*@}*/
#ifdef __cplusplus
}
#endif
#endif /* !__ASSEMBLER__ */
#endif /* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */
#endif /* !_AVR_EEPROM_H_ */

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/* Copyright (c) 2007, Atmel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
/* avr/fuse.h - Fuse API */
#ifndef _AVR_FUSE_H_
#define _AVR_FUSE_H_ 1
/* This file must be explicitly included by <avr/io.h>. */
#if !defined(_AVR_IO_H_)
#error "You must #include <avr/io.h> and not <avr/fuse.h> by itself."
#endif
/** \file */
/** \defgroup avr_fuse <avr/fuse.h>: Fuse Support
\par Introduction
The Fuse API allows a user to specify the fuse settings for the specific
AVR device they are compiling for. These fuse settings will be placed
in a special section in the ELF output file, after linking.
Programming tools can take advantage of the fuse information embedded in
the ELF file, by extracting this information and determining if the fuses
need to be programmed before programming the Flash and EEPROM memories.
This also allows a single ELF file to contain all the
information needed to program an AVR.
To use the Fuse API, include the <avr/io.h> header file, which in turn
automatically includes the individual I/O header file and the <avr/fuse.h>
file. These other two files provides everything necessary to set the AVR
fuses.
\par Fuse API
Each I/O header file must define the FUSE_MEMORY_SIZE macro which is
defined to the number of fuse bytes that exist in the AVR device.
A new type, __fuse_t, is defined as a structure. The number of fields in
this structure are determined by the number of fuse bytes in the
FUSE_MEMORY_SIZE macro.
If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type
unsigned char.
If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type
unsigned char.
If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended,
of type unsigned char.
If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array
of unsigned char with the size of the array being FUSE_MEMORY_SIZE.
A convenience macro, FUSEMEM, is defined as a GCC attribute for a
custom-named section of ".fuse".
A convenience macro, FUSES, is defined that declares a variable, __fuse, of
type __fuse_t with the attribute defined by FUSEMEM. This variable
allows the end user to easily set the fuse data.
\note If a device-specific I/O header file has previously defined FUSEMEM,
then FUSEMEM is not redefined. If a device-specific I/O header file has
previously defined FUSES, then FUSES is not redefined.
Each AVR device I/O header file has a set of defined macros which specify the
actual fuse bits available on that device. The AVR fuses have inverted
values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a
programmed (enabled) bit. The defined macros for each individual fuse
bit represent this in their definition by a bit-wise inversion of a mask.
For example, the FUSE_EESAVE fuse in the ATmega128 is defined as:
\code
#define FUSE_EESAVE ~_BV(3)
\endcode
\note The _BV macro creates a bit mask from a bit number. It is then
inverted to represent logical values for a fuse memory byte.
To combine the fuse bits macros together to represent a whole fuse byte,
use the bitwise AND operator, like so:
\code
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN)
\endcode
Each device I/O header file also defines macros that provide default values
for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low
Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT
is defined for an Extended Fuse byte.
If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that
provide default values for each fuse byte like so:
FUSE0_DEFAULT
FUSE1_DEFAULT
FUSE2_DEFAULT
FUSE3_DEFAULT
FUSE4_DEFAULT
....
\par API Usage Example
Putting all of this together is easy. Using C99's designated initializers:
\code
#include <avr/io.h>
FUSES =
{
.low = LFUSE_DEFAULT,
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
.extended = EFUSE_DEFAULT,
};
int main(void)
{
return 0;
}
\endcode
Or, using the variable directly instead of the FUSES macro,
\code
#include <avr/io.h>
__fuse_t __fuse __attribute__((section (".fuse"))) =
{
.low = LFUSE_DEFAULT,
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
.extended = EFUSE_DEFAULT,
};
int main(void)
{
return 0;
}
\endcode
If you are compiling in C++, you cannot use the designated intializers so
you must do:
\code
#include <avr/io.h>
FUSES =
{
LFUSE_DEFAULT, // .low
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high
EFUSE_DEFAULT, // .extended
};
int main(void)
{
return 0;
}
\endcode
However there are a number of caveats that you need to be aware of to
use this API properly.
Be sure to include <avr/io.h> to get all of the definitions for the API.
The FUSES macro defines a global variable to store the fuse data. This
variable is assigned to its own linker section. Assign the desired fuse
values immediately in the variable initialization.
The .fuse section in the ELF file will get its values from the initial
variable assignment ONLY. This means that you can NOT assign values to
this variable in functions and the new values will not be put into the
ELF .fuse section.
The global variable is declared in the FUSES macro has two leading
underscores, which means that it is reserved for the "implementation",
meaning the library, so it will not conflict with a user-named variable.
You must initialize ALL fields in the __fuse_t structure. This is because
the fuse bits in all bytes default to a logical 1, meaning unprogrammed.
Normal uninitialized data defaults to all locgial zeros. So it is vital that
all fuse bytes are initialized, even with default data. If they are not,
then the fuse bits may not programmed to the desired settings.
Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
your linker command line to have the correct device selected and to have
the correct I/O header file included when you include <avr/io.h>.
You can print out the contents of the .fuse section in the ELF file by
using this command line:
\code
avr-objdump -s -j .fuse <ELF file>
\endcode
The section contents shows the address on the left, then the data going from
lower address to a higher address, left to right.
*/
#if !(defined(__ASSEMBLER__) || defined(__DOXYGEN__))
#ifndef FUSEMEM
#define FUSEMEM __attribute__((__used__, __section__ (".fuse")))
#endif
#if FUSE_MEMORY_SIZE > 3
typedef struct
{
unsigned char byte[FUSE_MEMORY_SIZE];
} __fuse_t;
#elif FUSE_MEMORY_SIZE == 3
typedef struct
{
unsigned char low;
unsigned char high;
unsigned char extended;
} __fuse_t;
#elif FUSE_MEMORY_SIZE == 2
typedef struct
{
unsigned char low;
unsigned char high;
} __fuse_t;
#elif FUSE_MEMORY_SIZE == 1
typedef struct
{
unsigned char byte;
} __fuse_t;
#endif
#if !defined(FUSES)
#if defined(__AVR_XMEGA__)
#define FUSES NVM_FUSES_t __fuse FUSEMEM
#else
#define FUSES __fuse_t __fuse FUSEMEM
#endif
#endif
#endif /* !(__ASSEMBLER__ || __DOXYGEN__) */
#endif /* _AVR_FUSE_H_ */

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/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz
Copyright (c) 2007, Dean Camera
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
#ifndef _AVR_INTERRUPT_H_
#define _AVR_INTERRUPT_H_
#include <avr/io.h>
#if !defined(__DOXYGEN__) && !defined(__STRINGIFY)
/* Auxiliary macro for ISR_ALIAS(). */
#define __STRINGIFY(x) #x
#endif /* !defined(__DOXYGEN__) */
/**
\file
\@{
*/
/** \name Global manipulation of the interrupt flag
The global interrupt flag is maintained in the I bit of the status
register (SREG).
Handling interrupts frequently requires attention regarding atomic
access to objects that could be altered by code running within an
interrupt context, see <util/atomic.h>.
Frequently, interrupts are being disabled for periods of time in
order to perform certain operations without being disturbed; see
\ref optim_code_reorder for things to be taken into account with
respect to compiler optimizations.
*/
#if defined(__DOXYGEN__)
/** \def sei()
\ingroup avr_interrupts
Enables interrupts by setting the global interrupt mask. This function
actually compiles into a single line of assembly, so there is no function
call overhead. However, the macro also implies a <i>memory barrier</i>
which can cause additional loss of optimization.
In order to implement atomic access to multi-byte objects,
consider using the macros from <util/atomic.h>, rather than
implementing them manually with cli() and sei().
*/
#define sei()
#else /* !DOXYGEN */
# define sei() __asm__ __volatile__ ("sei" ::: "memory")
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def cli()
\ingroup avr_interrupts
Disables all interrupts by clearing the global interrupt mask. This function
actually compiles into a single line of assembly, so there is no function
call overhead. However, the macro also implies a <i>memory barrier</i>
which can cause additional loss of optimization.
In order to implement atomic access to multi-byte objects,
consider using the macros from <util/atomic.h>, rather than
implementing them manually with cli() and sei().
*/
#define cli()
#else /* !DOXYGEN */
# define cli() __asm__ __volatile__ ("cli" ::: "memory")
#endif /* DOXYGEN */
/** \name Macros for writing interrupt handler functions */
#if defined(__DOXYGEN__)
/** \def ISR(vector [, attributes])
\ingroup avr_interrupts
Introduces an interrupt handler function (interrupt service
routine) that runs with global interrupts initially disabled
by default with no attributes specified.
The attributes are optional and alter the behaviour and resultant
generated code of the interrupt routine. Multiple attributes may
be used for a single function, with a space seperating each
attribute.
Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and
ISR_ALIASOF(vect).
\c vector must be one of the interrupt vector names that are
valid for the particular MCU type.
*/
# define ISR(vector, [attributes])
#else /* real code */
#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
# define __INTR_ATTRS used, externally_visible
#else /* GCC < 4.1 */
# define __INTR_ATTRS used
#endif
#ifdef __cplusplus
# define ISR(vector, ...) \
extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
void vector (void)
#else
# define ISR(vector, ...) \
void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
void vector (void)
#endif
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def SIGNAL(vector)
\ingroup avr_interrupts
Introduces an interrupt handler function that runs with global interrupts
initially disabled.
This is the same as the ISR macro without optional attributes.
\deprecated Do not use SIGNAL() in new code. Use ISR() instead.
*/
# define SIGNAL(vector)
#else /* real code */
#ifdef __cplusplus
# define SIGNAL(vector) \
extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS)); \
void vector (void)
#else
# define SIGNAL(vector) \
void vector (void) __attribute__ ((signal, __INTR_ATTRS)); \
void vector (void)
#endif
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def EMPTY_INTERRUPT(vector)
\ingroup avr_interrupts
Defines an empty interrupt handler function. This will not generate
any prolog or epilog code and will only return from the ISR. Do not
define a function body as this will define it for you.
Example:
\code EMPTY_INTERRUPT(ADC_vect);\endcode */
# define EMPTY_INTERRUPT(vector)
#else /* real code */
#ifdef __cplusplus
# define EMPTY_INTERRUPT(vector) \
extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS)); \
void vector (void) { __asm__ __volatile__ ("reti" ::); }
#else
# define EMPTY_INTERRUPT(vector) \
void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS)); \
void vector (void) { __asm__ __volatile__ ("reti" ::); }
#endif
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def ISR_ALIAS(vector, target_vector)
\ingroup avr_interrupts
Aliases a given vector to another one in the same manner as the
ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF
attribute macro however, this is compatible for all versions of
GCC rather than just GCC version 4.2 onwards.
\note This macro creates a trampoline function for the aliased
macro. This will result in a two cycle penalty for the aliased
vector compared to the ISR the vector is aliased to, due to the
JMP/RJMP opcode used.
\deprecated
For new code, the use of ISR(..., ISR_ALIASOF(...)) is
recommended.
Example:
\code
ISR(INT0_vect)
{
PORTB = 42;
}
ISR_ALIAS(INT1_vect, INT0_vect);
\endcode
*/
# define ISR_ALIAS(vector, target_vector)
#else /* real code */
#ifdef __cplusplus
# if defined(__AVR_MEGA__) && __AVR_MEGA__
# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
__attribute__((signal, naked, __INTR_ATTRS)); \
void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); }
# else /* !__AVR_MEGA */
# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
__attribute__((signal, naked, __INTR_ATTRS)); \
void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); }
# endif /* __AVR_MEGA__ */
#else /* !__cplusplus */
# if defined(__AVR_MEGA__) && __AVR_MEGA__
# define ISR_ALIAS(vector, tgt) void vector (void) \
__attribute__((signal, naked, __INTR_ATTRS)); \
void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); }
# else /* !__AVR_MEGA */
# define ISR_ALIAS(vector, tgt) void vector (void) \
__attribute__((signal, naked, __INTR_ATTRS)); \
void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); }
# endif /* __AVR_MEGA__ */
#endif /* __cplusplus */
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def reti()
\ingroup avr_interrupts
Returns from an interrupt routine, enabling global interrupts. This should
be the last command executed before leaving an ISR defined with the ISR_NAKED
attribute.
This macro actually compiles into a single line of assembly, so there is
no function call overhead.
*/
# define reti()
#else /* !DOXYGEN */
# define reti() __asm__ __volatile__ ("reti" ::)
#endif /* DOXYGEN */
#if defined(__DOXYGEN__)
/** \def BADISR_vect
\ingroup avr_interrupts
\code #include <avr/interrupt.h> \endcode
This is a vector which is aliased to __vector_default, the vector
executed when an ISR fires with no accompanying ISR handler. This
may be used along with the ISR() macro to create a catch-all for
undefined but used ISRs for debugging purposes.
*/
# define BADISR_vect
#else /* !DOXYGEN */
# define BADISR_vect __vector_default
#endif /* DOXYGEN */
/** \name ISR attributes */
#if defined(__DOXYGEN__)
/** \def ISR_BLOCK
\ingroup avr_interrupts
Identical to an ISR with no attributes specified. Global
interrupts are initially disabled by the AVR hardware when
entering the ISR, without the compiler modifying this state.
Use this attribute in the attributes parameter of the ISR macro.
*/
# define ISR_BLOCK
/** \def ISR_NOBLOCK
\ingroup avr_interrupts
ISR runs with global interrupts initially enabled. The interrupt
enable flag is activated by the compiler as early as possible
within the ISR to ensure minimal processing delay for nested
interrupts.
This may be used to create nested ISRs, however care should be
taken to avoid stack overflows, or to avoid infinitely entering
the ISR for those cases where the AVR hardware does not clear the
respective interrupt flag before entering the ISR.
Use this attribute in the attributes parameter of the ISR macro.
*/
# define ISR_NOBLOCK
/** \def ISR_NAKED
\ingroup avr_interrupts
ISR is created with no prologue or epilogue code. The user code is
responsible for preservation of the machine state including the
SREG register, as well as placing a reti() at the end of the
interrupt routine.
Use this attribute in the attributes parameter of the ISR macro.
*/
# define ISR_NAKED
/** \def ISR_ALIASOF(target_vector)
\ingroup avr_interrupts
The ISR is linked to another ISR, specified by the vect parameter.
This is compatible with GCC 4.2 and greater only.
Use this attribute in the attributes parameter of the ISR macro.
*/
# define ISR_ALIASOF(target_vector)
#else /* !DOXYGEN */
# define ISR_BLOCK
# define ISR_NOBLOCK __attribute__((interrupt))
# define ISR_NAKED __attribute__((naked))
# define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v))))
#endif /* DOXYGEN */
/* \@} */
#endif

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arduino/hardware/tools/avr/avr/include/avr/io.h
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/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
Copyright (c) 2007 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
/** \file */
/** \defgroup avr_io <avr/io.h>: AVR device-specific IO definitions
\code #include <avr/io.h> \endcode
This header file includes the apropriate IO definitions for the
device that has been specified by the <tt>-mmcu=</tt> compiler
command-line switch. This is done by diverting to the appropriate
file <tt>&lt;avr/io</tt><em>XXXX</em><tt>.h&gt;</tt> which should
never be included directly. Some register names common to all
AVR devices are defined directly within <tt>&lt;avr/common.h&gt;</tt>,
which is included in <tt>&lt;avr/io.h&gt;</tt>,
but most of the details come from the respective include file.
Note that this file always includes the following files:
\code
#include <avr/sfr_defs.h>
#include <avr/portpins.h>
#include <avr/common.h>
#include <avr/version.h>
\endcode
See \ref avr_sfr for more details about that header file.
Included are definitions of the IO register set and their
respective bit values as specified in the Atmel documentation.
Note that inconsistencies in naming conventions,
so even identical functions sometimes get different names on
different devices.
Also included are the specific names useable for interrupt
function definitions as documented
\ref avr_signames "here".
Finally, the following macros are defined:
- \b RAMEND
<br>
The last on-chip RAM address.
<br>
- \b XRAMEND
<br>
The last possible RAM location that is addressable. This is equal to
RAMEND for devices that do not allow for external RAM. For devices
that allow external RAM, this will be larger than RAMEND.
<br>
- \b E2END
<br>
The last EEPROM address.
<br>
- \b FLASHEND
<br>
The last byte address in the Flash program space.
<br>
- \b SPM_PAGESIZE
<br>
For devices with bootloader support, the flash pagesize
(in bytes) to be used for the \c SPM instruction.
- \b E2PAGESIZE
<br>
The size of the EEPROM page.
*/
#ifndef _AVR_IO_H_
#define _AVR_IO_H_
#include <avr/sfr_defs.h>
#if defined (__AVR_AT94K__)
# include <avr/ioat94k.h>
#elif defined (__AVR_AT43USB320__)
# include <avr/io43u32x.h>
#elif defined (__AVR_AT43USB355__)
# include <avr/io43u35x.h>
#elif defined (__AVR_AT76C711__)
# include <avr/io76c711.h>
#elif defined (__AVR_AT86RF401__)
# include <avr/io86r401.h>
#elif defined (__AVR_AT90PWM1__)
# include <avr/io90pwm1.h>
#elif defined (__AVR_AT90PWM2__)
# include <avr/io90pwmx.h>
#elif defined (__AVR_AT90PWM2B__)
# include <avr/io90pwm2b.h>
#elif defined (__AVR_AT90PWM3__)
# include <avr/io90pwmx.h>
#elif defined (__AVR_AT90PWM3B__)
# include <avr/io90pwm3b.h>
#elif defined (__AVR_AT90PWM216__)
# include <avr/io90pwm216.h>
#elif defined (__AVR_AT90PWM316__)
# include <avr/io90pwm316.h>
#elif defined (__AVR_AT90PWM161__)
# include <avr/io90pwm161.h>
#elif defined (__AVR_AT90PWM81__)
# include <avr/io90pwm81.h>
#elif defined (__AVR_ATmega8U2__)
# include <avr/iom8u2.h>
#elif defined (__AVR_ATmega16M1__)
# include <avr/iom16m1.h>
#elif defined (__AVR_ATmega16U2__)
# include <avr/iom16u2.h>
#elif defined (__AVR_ATmega16U4__)
# include <avr/iom16u4.h>
#elif defined (__AVR_ATmega32C1__)
# include <avr/iom32c1.h>
#elif defined (__AVR_ATmega32M1__)
# include <avr/iom32m1.h>
#elif defined (__AVR_ATmega32U2__)
# include <avr/iom32u2.h>
#elif defined (__AVR_ATmega32U4__)
# include <avr/iom32u4.h>
#elif defined (__AVR_ATmega32U6__)
# include <avr/iom32u6.h>
#elif defined (__AVR_ATmega64C1__)
# include <avr/iom64c1.h>
#elif defined (__AVR_ATmega64M1__)
# include <avr/iom64m1.h>
#elif defined (__AVR_ATmega128__)
# include <avr/iom128.h>
#elif defined (__AVR_ATmega128A__)
# include <avr/iom128a.h>
#elif defined (__AVR_ATmega1280__)
# include <avr/iom1280.h>
#elif defined (__AVR_ATmega1281__)
# include <avr/iom1281.h>
#elif defined (__AVR_ATmega1284__)
# include <avr/iom1284.h>
#elif defined (__AVR_ATmega1284P__)
# include <avr/iom1284p.h>
#elif defined (__AVR_ATmega128RFA1__)
# include <avr/iom128rfa1.h>
#elif defined (__AVR_ATmega1284RFR2__)
# include <avr/iom1284rfr2.h>
#elif defined (__AVR_ATmega128RFR2__)
# include <avr/iom128rfr2.h>
#elif defined (__AVR_ATmega2564RFR2__)
# include <avr/iom2564rfr2.h>
#elif defined (__AVR_ATmega256RFR2__)
# include <avr/iom256rfr2.h>
#elif defined (__AVR_ATmega2560__)
# include <avr/iom2560.h>
#elif defined (__AVR_ATmega2561__)
# include <avr/iom2561.h>
#elif defined (__AVR_AT90CAN32__)
# include <avr/iocan32.h>
#elif defined (__AVR_AT90CAN64__)
# include <avr/iocan64.h>
#elif defined (__AVR_AT90CAN128__)
# include <avr/iocan128.h>
#elif defined (__AVR_AT90USB82__)
# include <avr/iousb82.h>
#elif defined (__AVR_AT90USB162__)
# include <avr/iousb162.h>
#elif defined (__AVR_AT90USB646__)
# include <avr/iousb646.h>
#elif defined (__AVR_AT90USB647__)
# include <avr/iousb647.h>
#elif defined (__AVR_AT90USB1286__)
# include <avr/iousb1286.h>
#elif defined (__AVR_AT90USB1287__)
# include <avr/iousb1287.h>
#elif defined (__AVR_ATmega644RFR2__)
# include <avr/iom644rfr2.h>
#elif defined (__AVR_ATmega64RFR2__)
# include <avr/iom64rfr2.h>
#elif defined (__AVR_ATmega64__)
# include <avr/iom64.h>
#elif defined (__AVR_ATmega64A__)
# include <avr/iom64a.h>
#elif defined (__AVR_ATmega640__)
# include <avr/iom640.h>
#elif defined (__AVR_ATmega644__)
# include <avr/iom644.h>
#elif defined (__AVR_ATmega644A__)
# include <avr/iom644a.h>
#elif defined (__AVR_ATmega644P__)
# include <avr/iom644p.h>
#elif defined (__AVR_ATmega644PA__)
# include <avr/iom644pa.h>
#elif defined (__AVR_ATmega645__)
# include <avr/iom645.h>
#elif (defined __AVR_ATmega645A__)
#include <avr/iom645a.h>
#elif (defined __AVR_ATmega645P__)
#include <avr/iom645p.h>
#elif defined (__AVR_ATmega6450__)
# include <avr/iom6450.h>
#elif (defined __AVR_ATmega6450A__)
#include <avr/iom6450a.h>
#elif (defined __AVR_ATmega6450P__)
#include <avr/iom6450p.h>
#elif defined (__AVR_ATmega649__)
# include <avr/iom649.h>
#elif (defined __AVR_ATmega649A__)
#include <avr/iom649a.h>
#elif defined (__AVR_ATmega6490__)
# include <avr/iom6490.h>
#elif (defined __AVR_ATmega6490A__)
#include <avr/iom6490a.h>
#elif (defined __AVR_ATmega6490P__)
#include <avr/iom6490p.h>
#elif defined (__AVR_ATmega649P__)
# include <avr/iom649p.h>
#elif defined (__AVR_ATmega64HVE__)
# include <avr/iom64hve.h>
#elif defined (__AVR_ATmega64HVE2__)
# include <avr/iom64hve2.h>
#elif defined (__AVR_ATmega103__)
# include <avr/iom103.h>
#elif defined (__AVR_ATmega32__)
# include <avr/iom32.h>
#elif defined (__AVR_ATmega32A__)
# include <avr/iom32a.h>
#elif defined (__AVR_ATmega323__)
# include <avr/iom323.h>
#elif defined (__AVR_ATmega324P__)
# include <avr/iom324p.h>
#elif (defined __AVR_ATmega324A__)
#include <avr/iom324a.h>
#elif defined (__AVR_ATmega324PA__)
# include <avr/iom324pa.h>
#elif defined (__AVR_ATmega325__)
# include <avr/iom325.h>
#elif (defined __AVR_ATmega325A__)
#include <avr/iom325a.h>
#elif defined (__AVR_ATmega325P__)
# include <avr/iom325p.h>
#elif defined (__AVR_ATmega325PA__)
# include <avr/iom325pa.h>
#elif defined (__AVR_ATmega3250__)
# include <avr/iom3250.h>
#elif (defined __AVR_ATmega3250A__)
#include <avr/iom3250a.h>
#elif defined (__AVR_ATmega3250P__)
# include <avr/iom3250p.h>
#elif defined (__AVR_ATmega3250PA__)
# include <avr/iom3250pa.h>
#elif defined (__AVR_ATmega328P__)
# include <avr/iom328p.h>
#elif (defined __AVR_ATmega328__)
#include <avr/iom328.h>
#elif defined (__AVR_ATmega329__)
# include <avr/iom329.h>
#elif (defined __AVR_ATmega329A__)
#include <avr/iom329a.h>
#elif defined (__AVR_ATmega329P__)
# include <avr/iom329p.h>
#elif (defined __AVR_ATmega329PA__)
#include <avr/iom329pa.h>
#elif (defined __AVR_ATmega3290PA__)
#include <avr/iom3290pa.h>
#elif defined (__AVR_ATmega3290__)
# include <avr/iom3290.h>
#elif (defined __AVR_ATmega3290A__)
#include <avr/iom3290a.h>
#elif defined (__AVR_ATmega3290P__)
# include <avr/iom3290.h>
#elif defined (__AVR_ATmega32HVB__)
# include <avr/iom32hvb.h>
#elif defined (__AVR_ATmega32HVBREVB__)
# include <avr/iom32hvbrevb.h>
#elif defined (__AVR_ATmega406__)
# include <avr/iom406.h>
#elif defined (__AVR_ATmega16__)
# include <avr/iom16.h>
#elif defined (__AVR_ATmega16A__)
# include <avr/iom16a.h>
#elif defined (__AVR_ATmega161__)
# include <avr/iom161.h>
#elif defined (__AVR_ATmega162__)
# include <avr/iom162.h>
#elif defined (__AVR_ATmega163__)
# include <avr/iom163.h>
#elif defined (__AVR_ATmega164P__)
# include <avr/iom164p.h>
#elif (defined __AVR_ATmega164A__)
#include <avr/iom164a.h>
#elif defined (__AVR_ATmega164PA__)
# include <avr/iom164pa.h>
#elif defined (__AVR_ATmega165__)
# include <avr/iom165.h>
#elif defined (__AVR_ATmega165A__)
# include <avr/iom165a.h>
#elif defined (__AVR_ATmega165P__)
# include <avr/iom165p.h>
#elif defined (__AVR_ATmega165PA__)
# include <avr/iom165pa.h>
#elif defined (__AVR_ATmega168__)
# include <avr/iom168.h>
#elif defined (__AVR_ATmega168A__)
# include <avr/iom168a.h>
#elif defined (__AVR_ATmega168P__)
# include <avr/iom168p.h>
#elif defined (__AVR_ATmega168PA__)
# include <avr/iom168pa.h>
#elif defined (__AVR_ATmega168PB__)
# include <avr/iom168pb.h>
#elif defined (__AVR_ATmega169__)
# include <avr/iom169.h>
#elif (defined __AVR_ATmega169A__)
#include <avr/iom169a.h>
#elif defined (__AVR_ATmega169P__)
# include <avr/iom169p.h>
#elif defined (__AVR_ATmega169PA__)
# include <avr/iom169pa.h>
#elif defined (__AVR_ATmega8HVA__)
# include <avr/iom8hva.h>
#elif defined (__AVR_ATmega16HVA__)
# include <avr/iom16hva.h>
#elif defined (__AVR_ATmega16HVA2__)
# include <avr/iom16hva2.h>
#elif defined (__AVR_ATmega16HVB__)
# include <avr/iom16hvb.h>
#elif defined (__AVR_ATmega16HVBREVB__)
# include <avr/iom16hvbrevb.h>
#elif defined (__AVR_ATmega8__)
# include <avr/iom8.h>
#elif defined (__AVR_ATmega8A__)
# include <avr/iom8a.h>
#elif defined (__AVR_ATmega48__)
# include <avr/iom48.h>
#elif defined (__AVR_ATmega48A__)
# include <avr/iom48a.h>
#elif defined (__AVR_ATmega48PA__)
# include <avr/iom48pa.h>
#elif defined (__AVR_ATmega48PB__)
# include <avr/iom48pb.h>
#elif defined (__AVR_ATmega48P__)
# include <avr/iom48p.h>
#elif defined (__AVR_ATmega88__)
# include <avr/iom88.h>
#elif defined (__AVR_ATmega88A__)
# include <avr/iom88a.h>
#elif defined (__AVR_ATmega88P__)
# include <avr/iom88p.h>
#elif defined (__AVR_ATmega88PA__)
# include <avr/iom88pa.h>
#elif defined (__AVR_ATmega88PB__)
# include <avr/iom88pb.h>
#elif defined (__AVR_ATmega8515__)
# include <avr/iom8515.h>
#elif defined (__AVR_ATmega8535__)
# include <avr/iom8535.h>
#elif defined (__AVR_AT90S8535__)
# include <avr/io8535.h>
#elif defined (__AVR_AT90C8534__)
# include <avr/io8534.h>
#elif defined (__AVR_AT90S8515__)
# include <avr/io8515.h>
#elif defined (__AVR_AT90S4434__)
# include <avr/io4434.h>
#elif defined (__AVR_AT90S4433__)
# include <avr/io4433.h>
#elif defined (__AVR_AT90S4414__)
# include <avr/io4414.h>
#elif defined (__AVR_ATtiny22__)
# include <avr/iotn22.h>
#elif defined (__AVR_ATtiny26__)
# include <avr/iotn26.h>
#elif defined (__AVR_AT90S2343__)
# include <avr/io2343.h>
#elif defined (__AVR_AT90S2333__)
# include <avr/io2333.h>
#elif defined (__AVR_AT90S2323__)
# include <avr/io2323.h>
#elif defined (__AVR_AT90S2313__)
# include <avr/io2313.h>
#elif defined (__AVR_ATtiny4__)
# include <avr/iotn4.h>
#elif defined (__AVR_ATtiny5__)
# include <avr/iotn5.h>
#elif defined (__AVR_ATtiny9__)
# include <avr/iotn9.h>
#elif defined (__AVR_ATtiny10__)
# include <avr/iotn10.h>
#elif defined (__AVR_ATtiny20__)
# include <avr/iotn20.h>
#elif defined (__AVR_ATtiny40__)
# include <avr/iotn40.h>
#elif defined (__AVR_ATtiny2313__)
# include <avr/iotn2313.h>
#elif defined (__AVR_ATtiny2313A__)
# include <avr/iotn2313a.h>
#elif defined (__AVR_ATtiny13__)
# include <avr/iotn13.h>
#elif defined (__AVR_ATtiny13A__)
# include <avr/iotn13a.h>
#elif defined (__AVR_ATtiny25__)
# include <avr/iotn25.h>
#elif defined (__AVR_ATtiny4313__)
# include <avr/iotn4313.h>
#elif defined (__AVR_ATtiny45__)
# include <avr/iotn45.h>
#elif defined (__AVR_ATtiny85__)
# include <avr/iotn85.h>
#elif defined (__AVR_ATtiny24__)
# include <avr/iotn24.h>
#elif defined (__AVR_ATtiny24A__)
# include <avr/iotn24a.h>
#elif defined (__AVR_ATtiny44__)
# include <avr/iotn44.h>
#elif defined (__AVR_ATtiny44A__)
# include <avr/iotn44a.h>
#elif defined (__AVR_ATtiny441__)
# include <avr/iotn441.h>
#elif defined (__AVR_ATtiny84__)
# include <avr/iotn84.h>
#elif defined (__AVR_ATtiny84A__)
# include <avr/iotn84a.h>
#elif defined (__AVR_ATtiny841__)
# include <avr/iotn841.h>
#elif defined (__AVR_ATtiny261__)
# include <avr/iotn261.h>
#elif defined (__AVR_ATtiny261A__)
# include <avr/iotn261a.h>
#elif defined (__AVR_ATtiny461__)
# include <avr/iotn461.h>
#elif defined (__AVR_ATtiny461A__)
# include <avr/iotn461a.h>
#elif defined (__AVR_ATtiny861__)
# include <avr/iotn861.h>
#elif defined (__AVR_ATtiny861A__)
# include <avr/iotn861a.h>
#elif defined (__AVR_ATtiny43U__)
# include <avr/iotn43u.h>
#elif defined (__AVR_ATtiny48__)
# include <avr/iotn48.h>
#elif defined (__AVR_ATtiny88__)
# include <avr/iotn88.h>
#elif defined (__AVR_ATtiny828__)
# include <avr/iotn828.h>
#elif defined (__AVR_ATtiny87__)
# include <avr/iotn87.h>
#elif defined (__AVR_ATtiny167__)
# include <avr/iotn167.h>
#elif defined (__AVR_ATtiny1634__)
# include <avr/iotn1634.h>
#elif defined (__AVR_AT90SCR100__)
# include <avr/io90scr100.h>
#elif defined (__AVR_ATxmega8E5__)
# include <avr/iox8e5.h>
#elif defined (__AVR_ATxmega16A4__)
# include <avr/iox16a4.h>
#elif defined (__AVR_ATxmega16A4U__)
# include <avr/iox16a4u.h>
#elif defined (__AVR_ATxmega16C4__)
# include <avr/iox16c4.h>
#elif defined (__AVR_ATxmega16D4__)
# include <avr/iox16d4.h>
#elif defined (__AVR_ATxmega16E5__)
# include <avr/iox16e5.h>
#elif defined (__AVR_ATxmega32A4__)
# include <avr/iox32a4.h>
#elif defined (__AVR_ATxmega32A4U__)
# include <avr/iox32a4u.h>
#elif defined (__AVR_ATxmega32C3__)
# include <avr/iox32c3.h>
#elif defined (__AVR_ATxmega32C4__)
# include <avr/iox32c4.h>
#elif defined (__AVR_ATxmega32D3__)
# include <avr/iox32d3.h>
#elif defined (__AVR_ATxmega32D4__)
# include <avr/iox32d4.h>
#elif defined (__AVR_ATxmega32E5__)
# include <avr/iox32e5.h>
#elif defined (__AVR_ATxmega64A1__)
# include <avr/iox64a1.h>
#elif defined (__AVR_ATxmega64A1U__)
# include <avr/iox64a1u.h>
#elif defined (__AVR_ATxmega64A3__)
# include <avr/iox64a3.h>
#elif defined (__AVR_ATxmega64A3U__)
# include <avr/iox64a3u.h>
#elif defined (__AVR_ATxmega64A4U__)
# include <avr/iox64a4u.h>
#elif defined (__AVR_ATxmega64B1__)
# include <avr/iox64b1.h>
#elif defined (__AVR_ATxmega64B3__)
# include <avr/iox64b3.h>
#elif defined (__AVR_ATxmega64C3__)
# include <avr/iox64c3.h>
#elif defined (__AVR_ATxmega64D3__)
# include <avr/iox64d3.h>
#elif defined (__AVR_ATxmega64D4__)
# include <avr/iox64d4.h>
#elif defined (__AVR_ATxmega128A1__)
# include <avr/iox128a1.h>
#elif defined (__AVR_ATxmega128A1U__)
# include <avr/iox128a1u.h>
#elif defined (__AVR_ATxmega128A4U__)
# include <avr/iox128a4u.h>
#elif defined (__AVR_ATxmega128A3__)
# include <avr/iox128a3.h>
#elif defined (__AVR_ATxmega128A3U__)
# include <avr/iox128a3u.h>
#elif defined (__AVR_ATxmega128B1__)
# include <avr/iox128b1.h>
#elif defined (__AVR_ATxmega128B3__)
# include <avr/iox128b3.h>
#elif defined (__AVR_ATxmega128C3__)
# include <avr/iox128c3.h>
#elif defined (__AVR_ATxmega128D3__)
# include <avr/iox128d3.h>
#elif defined (__AVR_ATxmega128D4__)
# include <avr/iox128d4.h>
#elif defined (__AVR_ATxmega192A3__)
# include <avr/iox192a3.h>
#elif defined (__AVR_ATxmega192A3U__)
# include <avr/iox192a3u.h>
#elif defined (__AVR_ATxmega192C3__)
# include <avr/iox192c3.h>
#elif defined (__AVR_ATxmega192D3__)
# include <avr/iox192d3.h>
#elif defined (__AVR_ATxmega256A3__)
# include <avr/iox256a3.h>
#elif defined (__AVR_ATxmega256A3U__)
# include <avr/iox256a3u.h>
#elif defined (__AVR_ATxmega256A3B__)
# include <avr/iox256a3b.h>
#elif defined (__AVR_ATxmega256A3BU__)
# include <avr/iox256a3bu.h>
#elif defined (__AVR_ATxmega256C3__)
# include <avr/iox256c3.h>
#elif defined (__AVR_ATxmega256D3__)
# include <avr/iox256d3.h>
#elif defined (__AVR_ATxmega384C3__)
# include <avr/iox384c3.h>
#elif defined (__AVR_ATxmega384D3__)
# include <avr/iox384d3.h>
#elif defined (__AVR_ATA5702M322__)
# include <avr/ioa5702m322.h>
#elif defined (__AVR_ATA5782__)
# include <avr/ioa5782.h>
#elif defined (__AVR_ATA5790__)
# include <avr/ioa5790.h>
#elif defined (__AVR_ATA5790N__)
# include <avr/ioa5790n.h>
#elif defined (__AVR_ATA5791__)
# include <avr/ioa5791.h>
#elif defined (__AVR_ATA5831__)
# include <avr/ioa5831.h>
#elif defined (__AVR_ATA5272__)
# include <avr/ioa5272.h>
#elif defined (__AVR_ATA5505__)
# include <avr/ioa5505.h>
#elif defined (__AVR_ATA5795__)
# include <avr/ioa5795.h>
#elif defined (__AVR_ATA6285__)
# include <avr/ioa6285.h>
#elif defined (__AVR_ATA6286__)
# include <avr/ioa6286.h>
#elif defined (__AVR_ATA6289__)
# include <avr/ioa6289.h>
#elif defined (__AVR_ATA6612C__)
# include <avr/ioa6612c.h>
#elif defined (__AVR_ATA6613C__)
# include <avr/ioa6613c.h>
#elif defined (__AVR_ATA6614Q__)
# include <avr/ioa6614q.h>
#elif defined (__AVR_ATA6616C__)
# include <avr/ioa6616c.h>
#elif defined (__AVR_ATA6617C__)
# include <avr/ioa6617c.h>
#elif defined (__AVR_ATA664251__)
# include <avr/ioa664251.h>
#elif defined (__AVR_ATA8210__)
# include <avr/ioa8210.h>
#elif defined (__AVR_ATA8510__)
# include <avr/ioa8510.h>
/* avr1: the following only supported for assembler programs */
#elif defined (__AVR_ATtiny28__)
# include <avr/iotn28.h>
#elif defined (__AVR_AT90S1200__)
# include <avr/io1200.h>
#elif defined (__AVR_ATtiny15__)
# include <avr/iotn15.h>
#elif defined (__AVR_ATtiny12__)
# include <avr/iotn12.h>
#elif defined (__AVR_ATtiny11__)
# include <avr/iotn11.h>
#elif defined (__AVR_M3000__)
# include <avr/iom3000.h>
#elif defined (__AVR_ATmega4809__)
# include <avr/iom4809.h>
#elif defined (__AVR_ATmega4808__)
# include <avr/iom4808.h>
#elif defined (__AVR_ATmega328PB__)
# include <avr/iom328pb.h>
#elif defined (__AVR_ATmega324PB__)
# include <avr/iom324pb.h>
#elif defined (__AVR_ATmega3209__)
# include <avr/iom3209.h>
#elif defined (__AVR_ATmega3208__)
# include <avr/iom3208.h>
#elif defined (__AVR_DEV_LIB_NAME__)
# define __concat__(a,b) a##b
# define __header1__(a,b) __concat__(a,b)
# define __AVR_DEVICE_HEADER__ <avr/__header1__(io,__AVR_DEV_LIB_NAME__).h>
# include __AVR_DEVICE_HEADER__
#else
# if !defined(__COMPILING_AVR_LIBC__)
# warning "device type not defined"
# endif
#endif
#include <avr/portpins.h>
#include <avr/common.h>
#include <avr/version.h>
#if __AVR_ARCH__ >= 100
# include <avr/xmega.h>
#endif
/* Include fuse.h after individual IO header files. */
#include <avr/fuse.h>
/* Include lock.h after individual IO header files. */
#include <avr/lock.h>
#endif /* _AVR_IO_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io1200.h - definitions for AT90S1200 */
#ifndef _AVR_IO1200_H_
#define _AVR_IO1200_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io1200.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
#endif
/* I/O registers */
/* 0x00..0x07 reserved */
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* 0x09..0x0F reserved */
#define PIND _SFR_IO8(0x10)
#define DDRD _SFR_IO8(0x11)
#define PORTD _SFR_IO8(0x12)
/* 0x13..0x15 reserved */
#define PINB _SFR_IO8(0x16)
#define DDRB _SFR_IO8(0x17)
#define PORTB _SFR_IO8(0x18)
/* 0x19..0x1B reserved */
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* 0x1F..0x20 reserved */
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* 0x22..0x31 reserved */
#define TCNT0 _SFR_IO8(0x32)
#define TCCR0 _SFR_IO8(0x33)
/* 0x34 reserved */
#define MCUCR _SFR_IO8(0x35)
/* 0x36..0x37 reserved */
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK Register */
#define TIMSK _SFR_IO8(0x39)
/* 0x3A reserved */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C..0x3E reserved */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 2
#define TIMER0_OVF_vect _VECTOR(2)
#define SIG_OVERFLOW0 _VECTOR(2)
/* Analog Comparator */
#define ANA_COMP_vect_num 3
#define ANA_COMP_vect _VECTOR(3)
#define SIG_COMPARATOR _VECTOR(3)
#define _VECTORS_SIZE 8
/* Bit numbers */
/* GIMSK */
#define INT0 6
/* TIMSK */
#define TOIE0 1
/* TIFR */
#define TOV0 1
/* MCUCR */
#define SE 5
#define SM 4
#define ISC01 1
#define ISC00 0
/* TCCR0 */
#define CS02 2
#define CS01 1
#define CS00 0
/* WDTCR */
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* EECR */
#undef EEMWE
/*
PB7 = SCK
PB6 = MISO
PB5 = MOSI
PB1 = AIN1
PB0 = AIN0
*/
/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* PORTD */
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* DDRD */
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PIND */
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* ACSR */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIS1 1
#define ACIS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
#undef ZH
#define RAMSTART 0x60
/* Last memory addresses */
#define RAMEND 0x1F
#define XRAMEND 0x0
#define E2END 0x3F
#define E2PAGESIZE 0
#define FLASHEND 0x3FF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_RCEN (unsigned char)~_BV(0)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x90
#define SIGNATURE_2 0x01
#endif /* _AVR_IO1200_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io2313.h - definitions for AT90S2313 */
#ifndef _AVR_IO2313_H_
#define _AVR_IO2313_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io2313.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Output Compare Register 1 */
#define OCR1 _SFR_IO16(0x2A)
#define OCR1L _SFR_IO8(0x2A)
#define OCR1H _SFR_IO8(0x2B)
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C..0x3D SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT1_vect_num 3
#define TIMER1_CAPT1_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match */
#define TIMER1_COMP1_vect_num 4
#define TIMER1_COMP1_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF1_vect_num 5
#define TIMER1_OVF1_vect _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(5)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF0_vect_num 6
#define TIMER0_OVF0_vect _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(6)
/* UART, Rx Complete */
#define UART_RX_vect_num 7
#define UART_RX_vect _VECTOR(7)
#define SIG_UART_RECV _VECTOR(7)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 8
#define UART_UDRE_vect _VECTOR(8)
#define SIG_UART_DATA _VECTOR(8)
/* UART, Tx Complete */
#define UART_TX_vect_num 9
#define UART_TX_vect _VECTOR(9)
#define SIG_UART_TRANS _VECTOR(9)
/* Analog Comparator */
#define ANA_COMP_vect_num 10
#define ANA_COMP_vect _VECTOR(10)
#define SIG_COMPARATOR _VECTOR(10)
#define _VECTORS_SIZE 22
/*
* The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1A 6
#define TICIE 3 /* old name */
#define TICIE1 3
#define TOIE0 1
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1A 6
#define ICF1 3
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* EEPROM Control Register */
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port D */
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF
#define XRAMEND RAMEND
#define E2END 0x7F
#define E2PAGESIZE 0
#define FLASHEND 0x07FF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_FSTRT (unsigned char)~_BV(0)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x91
#define SIGNATURE_2 0x01
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO2313_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io2323.h - definitions for AT90S2323 */
#ifndef _AVR_IO2323_H_
#define _AVR_IO2323_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io2323.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF0_vect_num 2
#define TIMER0_OVF0_vect _VECTOR(2)
#define SIG_OVERFLOW0 _VECTOR(2)
#define _VECTORS_SIZE 6
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt MaSK register */
#define INT0 6
#define INTF0 6
/* General Interrupt Flag Register */
#define TOIE0 1
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/*
PB2 = SCK/T0
PB1 = MISO/INT0
PB0 = MOSI
*/
/* Data Register, Port B */
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF
#define XRAMEND RAMEND
#define E2END 0x7F
#define E2PAGESIZE 0
#define FLASHEND 0x07FF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_FSTRT (unsigned char)~_BV(0)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x91
#define SIGNATURE_2 0x02
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO2323_H_ */
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x91
#define SIGNATURE_2 0x02

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arduino/hardware/tools/avr/avr/include/avr/io2333.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io2333.h - definitions for AT90S2333 */
#ifndef _AVR_IO2333_H_
#define _AVR_IO2333_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io2333.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* UART Baud Rate Register high */
#define UBRRH _SFR_IO8(0x03)
/* ADC Data register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and Status Register */
#define ADCSR _SFR_IO8(0x06)
/* ADC MUX */
#define ADMUX _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control/Status Registers */
#define UCSRB _SFR_IO8(0x0A)
#define UCSRA _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register A */
#define OCR1 _SFR_IO16(0x2A)
#define OCR1L _SFR_IO8(0x2A)
#define OCR1H _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter Capture Event */
#define TIMER1_CAPT_vect_num 3
#define TIMER1_CAPT_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match */
#define TIMER1_COMP_vect_num 4
#define TIMER1_COMP_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 5
#define TIMER1_OVF_vect _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(5)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 6
#define TIMER0_OVF_vect _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(6)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 7
#define SPI_STC_vect _VECTOR(7)
#define SIG_SPI _VECTOR(7)
/* UART, Rx Complete */
#define UART_RX_vect_num 8
#define UART_RX_vect _VECTOR(8)
#define SIG_UART_RECV _VECTOR(8)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 9
#define UART_UDRE_vect _VECTOR(9)
#define SIG_UART_DATA _VECTOR(9)
/* UART, Tx Complete */
#define UART_TX_vect_num 10
#define UART_TX_vect _VECTOR(10)
#define SIG_UART_TRANS _VECTOR(10)
/* ADC Conversion Complete */
#define ADC_vect_num 11
#define ADC_vect _VECTOR(11)
#define SIG_ADC _VECTOR(11)
/* EEPROM Ready */
#define EE_RDY_vect_num 12
#define EE_RDY_vect _VECTOR(12)
#define SIG_EEPROM_READY _VECTOR(12)
/* Analog Comparator */
#define ANA_COMP_vect_num 13
#define ANA_COMP_vect _VECTOR(13)
#define SIG_COMPARATOR _VECTOR(13)
#define _VECTORS_SIZE 28
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* MCU general Status Register */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1 6
#define TICIE1 3
#define TOIE0 1
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1 6
#define ICF1 3
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM11 7
#define COM10 6
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
#define MPCM 0
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define AINBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADC MUX */
#define ACDBG 6
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADC Control and Status Register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* Data Register, Port B */
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF /*Last On-Chip SRAM location*/
#define XRAMEND RAMEND
#define E2END 0x7F
#define FLASHEND 0x7FF
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO2333_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io2343.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io2343.h - definitions for AT90S2343 */
#ifndef _AVR_IO2343_H_
#define _AVR_IO2343_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io2343.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF0_vect_num 2
#define TIMER0_OVF0_vect _VECTOR(2)
#define SIG_OVERFLOW0 _VECTOR(2)
#define _VECTORS_SIZE 6
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt MaSK register */
#define INT0 6
#define INTF0 6
/* General Interrupt Flag Register */
#define TOIE0 1
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC01 1
#define ISC00 0
/* MCU Status Register */
#define PORF 0
#define EXTRF 1
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/*
PB3 = CLOCK
PB2 = SCK/T0
PB1 = MISO/INT0
PB0 = MOSI
*/
/* Data Register, Port B */
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF
#define XRAMEND RAMEND
#define E2END 0x7F
#define E2PAGESIZE 0
#define FLASHEND 0x07FF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_RCEN (unsigned char)~_BV(0)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x91
#define SIGNATURE_2 0x03
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO2343_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io43u32x.h
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/* Copyright (c) 2003,2005 Keith Gudger
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */
/* avr/io43u32x.h - definitions for AT43USB32x */
#ifndef _AVR_IO43U32X_H_
#define _AVR_IO43U32X_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io43u32x.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* Input Pins, Port E */ // new port for 43324/6
#define PINE _SFR_IO8(0x01)
/* Data Direction Register, Port E */
#define DDRE _SFR_IO8(0x02)
/* Data Register, Port E */
#define PORTE _SFR_IO8(0x03)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* 0x1C..0x1F reserved */
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Control Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt Mask register */
#define GIMSK _SFR_IO8(0x3B)
/* Interrupt vectors */
#define SIG_INTERRUPT0 _VECTOR(1)
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_TIMER1_CAPT1 _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(7)
#define SIG_SPI _VECTOR(8)
#define SIG_UART_RECV _VECTOR(9)
#define SIG_UART_DATA _VECTOR(10)
#define SIG_UART_TRANS _VECTOR(11)
#define SIG_USB_INT _VECTOR(12)
#define _VECTORS_SIZE 52
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* Timer/Counter Interrupt MaSK register */
#define TICIE1 3
#define OCIE1A 6
#define OCIE1B 5
#define TOIE1 7
#define TOIE0 1
/* Timer/Counter Interrupt Flag Register */
#define ICF1 3
#define OCF1A 6
#define OCF1B 5
#define TOV1 7
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* Data Register, Port E */
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
/* Data Direction Register, Port E */
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* Input Pins, Port E */
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x025F /*Last On-Chip SRAM Location*/
#define XRAMEND RAMEND
#define E2END 0x0000
/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory,
but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */
#define FLASHEND 0x0FFFF
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_43USB32X_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io43u35x.h
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/* Copyright (c) 2003,2005 Keith Gudger
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */
/* avr/io43u35x.h - definitions for AT43USB35x */
#ifndef _AVR_IO43U35X_H_
#define _AVR_IO43U35X_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io43u35x.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* ADC Data Register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x02)
#endif
#define ADCW _SFR_IO16(0x02)
#define ADCL _SFR_IO8(0x02)
#define ADCH _SFR_IO8(0x03)
/* ADC Control and status register */
#define ADCSR _SFR_IO8(0x07)
/* ADC Multiplexer select */
#define ADMUX _SFR_IO8(0x08)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* Input Pins, Port F */
#define PINF _SFR_IO8(0x04)
/* Data Direction Register, Port F */
#define DDRF _SFR_IO8(0x05)
/* Data Register, Port F */
#define PORTF _SFR_IO8(0x06)
/* Input Pins, Port E */
#define PINE _SFR_IO8(0x01)
/* Data Direction Register, Port E */
#define DDRE _SFR_IO8(0x02)
/* Data Register, Port E */
#define PORTE _SFR_IO8(0x03)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* 0x1C..0x1F reserved */
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Control Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt Mask register */
#define GIMSK _SFR_IO8(0x3B)
/* Interrupt vectors */
#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_TIMER1_CAPT1 _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(7)
#define SIG_SPI _VECTOR(8)
/* 9, 10: reserved */
#define SIG_ADC _VECTOR(11)
#define SIG_USB_INT _VECTOR(12)
#define _VECTORS_SIZE 52
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* Timer/Counter Interrupt MaSK register */
#define TICIE1 3
#define OCIE1A 6
#define OCIE1B 5
#define TOIE1 7
#define TOIE0 1
/* Timer/Counter Interrupt Flag Register */
#define ICF1 3
#define OCF1A 6
#define OCF1B 5
#define TOV1 7
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* Data Register, Port F */
#define PF3 3
#define PF2 2
#define PF1 1
#define PF0 0
/* Data Direction Register, Port F */
#define DDF3 3
#define DDF2 2
#define DDF1 1
/* Input Pins, Port F */
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* ADC Multiplexer select */
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADC Control and Status Register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x045F /*Last On-Chip SRAM Location*/
#define XRAMEND RAMEND
#define E2END 0x0000
#define FLASHEND 0x5FFF
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_43USB355_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io4414.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io4414.h - definitions for AT90S4414 */
#ifndef _AVR_IO4414_H_
#define _AVR_IO4414_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io4414.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C..0x3D SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter Capture Event */
#define TIMER1_CAPT_vect_num 3
#define TIMER1_CAPT_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 4
#define TIMER1_COMPA_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Compare MatchB */
#define TIMER1_COMPB_vect_num 5
#define TIMER1_COMPB_vect _VECTOR(5)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 6
#define TIMER1_OVF_vect _VECTOR(6)
#define SIG_OVERFLOW1 _VECTOR(6)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 7
#define TIMER0_OVF_vect _VECTOR(7)
#define SIG_OVERFLOW0 _VECTOR(7)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 8
#define SPI_STC_vect _VECTOR(8)
#define SIG_SPI _VECTOR(8)
/* UART, Rx Complete */
#define UART_RX_vect_num 9
#define UART_RX_vect _VECTOR(9)
#define SIG_UART_RECV _VECTOR(9)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 10
#define UART_UDRE_vect _VECTOR(10)
#define SIG_UART_DATA _VECTOR(10)
/* UART, Tx Complete */
#define UART_TX_vect_num 11
#define UART_TX_vect _VECTOR(11)
#define SIG_UART_TRANS _VECTOR(11)
/* Analog Comparator */
#define ANA_COMP_vect_num 12
#define ANA_COMP_vect _VECTOR(12)
#define SIG_COMPARATOR _VECTOR(12)
#define _VECTORS_SIZE 26
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define TICIE1 3
#define TOIE0 1
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define ICF1 3
#define TOV0 1
/* MCU general Control Register */
#define SRE 7
#define SRW 6
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x15F /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0xFF
#define E2PAGESIZE 0
#define FLASHEND 0xFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */
#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x92
#define SIGNATURE_2 0x01
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO4414_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io4433.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io4433.h - definitions for AT90S4433 */
#ifndef _AVR_IO4433_H_
#define _AVR_IO4433_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io4433.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* UART Baud Rate Register high */
#define UBRRH _SFR_IO8(0x03)
/* ADC Data register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and Status Register */
#define ADCSR _SFR_IO8(0x06)
/* ADC MUX */
#define ADMUX _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control/Status Registers */
#define UCSRB _SFR_IO8(0x0A)
#define UCSRA _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register A */
#define OCR1 _SFR_IO16(0x2A)
#define OCR1L _SFR_IO8(0x2A)
#define OCR1H _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter Capture Event */
#define TIMER1_CAPT_vect_num 3
#define TIMER1_CAPT_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match */
#define TIMER1_COMP_vect_num 4
#define TIMER1_COMP_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 5
#define TIMER1_OVF_vect _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(5)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 6
#define TIMER0_OVF_vect _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(6)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 7
#define SPI_STC_vect _VECTOR(7)
#define SIG_SPI _VECTOR(7)
/* UART, Rx Complete */
#define UART_RX_vect_num 8
#define UART_RX_vect _VECTOR(8)
#define SIG_UART_RECV _VECTOR(8)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 9
#define UART_UDRE_vect _VECTOR(9)
#define SIG_UART_DATA _VECTOR(9)
/* UART, Tx Complete */
#define UART_TX_vect_num 10
#define UART_TX_vect _VECTOR(10)
#define SIG_UART_TRANS _VECTOR(10)
/* ADC Conversion Complete */
#define ADC_vect_num 11
#define ADC_vect _VECTOR(11)
#define SIG_ADC _VECTOR(11)
/* EEPROM Ready */
#define EE_RDY_vect_num 12
#define EE_RDY_vect _VECTOR(12)
#define SIG_EEPROM_READY _VECTOR(12)
/* Analog Comparator */
#define ANA_COMP_vect_num 13
#define ANA_COMP_vect _VECTOR(13)
#define SIG_COMPARATOR _VECTOR(13)
#define _VECTORS_SIZE 28
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* MCU general Status Register */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1 6
#define TICIE1 3
#define TOIE0 1
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1 6
#define ICF1 3
#define TOV0 1
/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM11 7
#define COM10 6
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
#define MPCM 0
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define AINBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADC MUX */
#define ACDBG 6
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADC Control and Status Register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* Data Register, Port B */
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF /*Last On-Chip SRAM location*/
#define XRAMEND RAMEND
#define E2END 0xFF
#define E2PAGESIZE 0
#define FLASHEND 0xFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_BODEN (unsigned char)~_BV(3)
#define FUSE_BODLEVEL (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x92
#define SIGNATURE_2 0x03
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO4433_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io4434.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io4434.h - definitions for AT90S4434 */
#ifndef _AVR_IO4434_H_
#define _AVR_IO4434_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io4434.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* ADC Data register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and Status Register */
#define ADCSR _SFR_IO8(0x06)
/* ADC MUX */
#define ADMUX _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO8(0x1E)
#define EEARL _SFR_IO8(0x1E)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Asynchronous mode Status Register */
#define ASSR _SFR_IO8(0x22)
/* Timer/Counter2 Output Compare Register */
#define OCR2 _SFR_IO8(0x23)
/* Timer/Counter 2 */
#define TCNT2 _SFR_IO8(0x24)
/* Timer/Counter 2 Control Register */
#define TCCR2 _SFR_IO8(0x25)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 3
#define TIMER2_COMP_vect _VECTOR(3)
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 4
#define TIMER2_OVF_vect _VECTOR(4)
#define SIG_OVERFLOW2 _VECTOR(4)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 5
#define TIMER1_CAPT_vect _VECTOR(5)
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 6
#define TIMER1_COMPA_vect _VECTOR(6)
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 7
#define TIMER1_COMPB_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 8
#define TIMER1_OVF_vect _VECTOR(8)
#define SIG_OVERFLOW1 _VECTOR(8)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 9
#define TIMER0_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW0 _VECTOR(9)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 10
#define SPI_STC_vect _VECTOR(10)
#define SIG_SPI _VECTOR(10)
/* UART, RX Complete */
#define UART_RX_vect_num 11
#define UART_RX_vect _VECTOR(11)
#define SIG_UART_RECV _VECTOR(11)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 12
#define UART_UDRE_vect _VECTOR(12)
#define SIG_UART_DATA _VECTOR(12)
/* UART, TX Complete */
#define UART_TX_vect_num 13
#define UART_TX_vect _VECTOR(13)
#define SIG_UART_TRANS _VECTOR(13)
/* ADC Conversion Complete */
#define ADC_vect_num 14
#define ADC_vect _VECTOR(14)
#define SIG_ADC _VECTOR(14)
/* EEPROM Ready */
#define EE_RDY_vect_num 15
#define EE_RDY_vect _VECTOR(15)
#define SIG_EEPROM_READY _VECTOR(15)
/* Analog Comparator */
#define ANA_COMP_vect_num 16
#define ANA_COMP_vect _VECTOR(16)
#define SIG_COMPARATOR _VECTOR(16)
#define _VECTORS_SIZE 34
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* MCU general Status Register */
#define EXTRF 1
#define PORF 0
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
#define TOIE0 0
/* Timer/Counter Interrupt Flag register */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
#define TOV0 0
/* MCU general Control Register */
#define SE 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter 2 Control Register */
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* Asynchronous mode Status Register */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADC MUX */
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADC Control and Status Register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x15F /*Last On-Chip SRAM location*/
#define XRAMEND RAMEND
#define E2END 0xFF
#define E2PAGESIZE 0
#define FLASHEND 0xFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */
#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x03
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_ADC _BV(SM0)
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
#endif /* _AVR_IO4434_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */
/* avr/io76c711.h - definitions for AT76C711 */
#ifndef _AVR_IO76C711_H_
#define _AVR_IO76C711_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io76c711.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* 0x00-0x0C reserved */
/* SPI */
#define SPCR _SFR_IO8(0x0D)
#define SPSR _SFR_IO8(0x0E)
#define SPDR _SFR_IO8(0x0F)
/* Port D */
#define PIND _SFR_IO8(0x10)
#define DDRD _SFR_IO8(0x11)
#define PORTD _SFR_IO8(0x12)
/* Peripheral Enable Register */
#define PERIPHEN _SFR_IO8(0x13)
/* Clock Control Register */
#define CLK_CNTR _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Port B */
#define PINB _SFR_IO8(0x16)
#define DDRB _SFR_IO8(0x17)
#define PORTB _SFR_IO8(0x18)
/* Port A */
#define PINA _SFR_IO8(0x19)
#define DDRA _SFR_IO8(0x1A)
#define PORTA _SFR_IO8(0x1B)
/* 0x1C-0x1F reserved */
#define IRDAMOD _SFR_IO8(0x20)
#define WDTCR _SFR_IO8(0x21)
/* 0x22-0x25 reserved */
/* Timer 1 */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
#define TCCR1B _SFR_IO8(0x2E)
#define TCCR1A _SFR_IO8(0x2F)
/* 0x30 reserved */
/* Timer 0 */
#define PRELD _SFR_IO8(0x31)
#define TCNT0 _SFR_IO8(0x32)
#define TCCR0 _SFR_IO8(0x33)
#define MCUSR _SFR_IO8(0x34)
#define MCUCR _SFR_IO8(0x35)
#define TIFR _SFR_IO8(0x36)
#define TIMSK _SFR_IO8(0x37)
/* 0x38 reserved */
#define EIMSK _SFR_IO8(0x39)
/* 0x3A-0x3C reserved */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
#define SIG_SUSPEND_RESUME _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(2)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
#define SIG_OVERFLOW1 _VECTOR(6)
#define SIG_OVERFLOW0 _VECTOR(7)
#define SIG_SPI _VECTOR(8)
#define SIG_TDMAC _VECTOR(9)
#define SIG_UART0 _VECTOR(10)
#define SIG_RDMAC _VECTOR(11)
#define SIG_USB_HW _VECTOR(12)
#define SIG_UART1 _VECTOR(13)
#define SIG_INTERRUPT1 _VECTOR(14)
#define _VECTORS_SIZE 60
/* Bit numbers */
/* EIMSK */
/* bits 7-4 reserved */
#define POL1 3
#define POL0 2
#define INT1 1
#define INT0 0
/* TIMSK */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
/* bit 4 reserved */
#define TICIE1 3
/* bit 2 reserved */
#define TOIE0 1
/* bit 0 reserved */
/* TIFR */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
/* bit 4 reserved */
#define ICF1 3
/* bit 2 reserved */
#define TOV0 1
/* bit 0 reserved */
/* MCUCR */
/* bits 7-6 reserved */
#define SE 5
#define SM1 4
#define SM0 3
/* bits 2-0 reserved */
/* MCUSR */
/* bits 7-2 reserved */
#define EXTRF 1
#define PORF 0
/* TCCR0 */
/* bits 7-6 reserved */
#define COM01 5
#define COM00 4
#define CTC0 3
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
/* bits 3-0 reserved */
/* TCCR1B */
#define ICNC1 7
#define ICES1 6
/* bits 5-4 reserved */
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* WDTCR */
/* bits 7-5 reserved */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* IRDAMOD */
/* bits 7-3 reserved */
#define POL 2
#define MODE 1
#define EN 0
/* PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* PINA */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/*
PB7 = SCK
PB6 = MISO
PB5 = MOSI
PB4 = SS#
PB2 = ICP
PB1 = T1
PB0 = T0
*/
/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* PORTC */
/* bits 7-4 reserved */
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/*
PD7 = INT1 / OC1B
PD6 = INT0 / OC1A
PD1 = TXD
PD0 = RXD
*/
/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* CLK_CNTR */
/* bits 7-5 reserved */
#define UOSC 4
#define UCK 3
#define IRCK 2
/* bits 1-0 reserved */
/* PERIPHEN */
/* bits 7-3 reserved */
#define IRDA 2
#define UART 1
#define USB 0
/* SPSR */
#define SPIF 7
#define WCOL 6
/* bits 5-0 reserved */
/* SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */
/* UART */
#define UART0_BASE 0x2020
#define UART1_BASE 0x2030
/* offsets from the base address */
#define US_RHR 0x00
#define US_THR 0x00
#define US_IER 0x01
#define US_FCR 0x02
#define US_PMR 0x03
#define US_MR 0x04
#define US_CSR 0x05
#define US_CR 0x06
#define US_BL 0x07
#define US_BM 0x08
#define US_RTO 0x09
#define US_TTG 0x0A
/* DMA */
#define DMA_BASE 0x2000
/* offsets from the base address */
#define TXTADL 0x01
#define TXPLL 0x03
#define TXPLM 0x04
#define TXTPLL 0x05
#define TXTPLM 0x06
#define RXTADL 0x07
#define RXTADMEN 0x08
#define RSPLL 0x09
#define RXPLM 0x0A
#define RXTPLL 0x0B
#define RXTPLM 0x0C
#define INTCST 0x0D
/* XXX DPORG register mentioned on page 20, but undocumented */
/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */
#define PROGRAM_MEMORY_CONTROL_BIT 0x2040
/* USB */
#define USB_BASE 0x1000
/* offsets from the base address */
#define FRM_NUM_H 0x0FD
#define FRM_NUM_L 0x0FC
#define GLB_STATE 0x0FB
#define SPRSR 0x0FA
#define SPRSIE 0x0F9
#define UISR 0x0F7
#define UIAR 0x0F5
#define FADDR 0x0F2
#define ENDPPGPG 0x0F1
#define ECR0 0x0EF
#define ECR1 0x0EE
#define ECR2 0x0ED
#define ECR3 0x0EC
#define ECR4 0x0EB
#define ECR5 0x0EA
#define ECR6 0x0E9
#define ECR7 0x0E8
#define CSR0 0x0DF
#define CSR1 0x0DE
#define CSR2 0x0DD
#define CSR3 0x0DC
#define CSR4 0x0DB
#define CSR5 0x0DA
#define CSR6 0x0D9
#define CSR7 0x0D8
#define FDR0 0x0CF
#define FDR1 0x0CE
#define FDR2 0x0CD
#define FDR3 0x0CC
#define FDR4 0x0CB
#define FDR5 0x0CA
#define FDR6 0x0C9
#define FDR7 0x0C8
#define FBYTE_CNT0_L 0x0BF
#define FBYTE_CNT1_L 0x0BE
#define FBYTE_CNT2_L 0x0BD
#define FBYTE_CNT3_L 0x0BC
#define FBYTE_CNT4_L 0x0BB
#define FBYTE_CNT5_L 0x0BA
#define FBYTE_CNT6_L 0x0B9
#define FBYTE_CNT7_L 0x0B8
#define FBYTE_CNT0_H 0x0AF
#define FBYTE_CNT1_H 0x0AE
#define FBYTE_CNT2_H 0x0AD
#define FBYTE_CNT3_H 0x0AC
#define FBYTE_CNT4_H 0x0AB
#define FBYTE_CNT5_H 0x0AA
#define FBYTE_CNT6_H 0x0A9
#define FBYTE_CNT7_H 0x0A8
#define SLP_MD_EN 0x100
#define IRQ_EN 0x101
#define IRQ_STAT 0x102
#define SUSP_WUP 0x103
#define PA_EN 0x104
#define USB_DMA_ADL 0x105
#define USB_DMA_ADH 0x106
#define USB_DMA_PLR 0x107
#define USB_DMA_EAD 0x108
#define USB_DMA_PLT 0x109
#define USB_DMA_EN 0x10A
/* Last memory addresses */
#define RAMSTART 0x60
#define RAMEND 0x07FF
#define XRAMEND RAMEND
#define E2END 0
#define FLASHEND 0x3FFF
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_ADC _BV(SM0)
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
/*
AT76C711 data space memory map (ranges not listed are reserved):
0x0000 - 0x001F - AVR registers
0x0020 - 0x005F - AVR I/O space
0x0060 - 0x07FF - AVR data SRAM
0x1000 - 0x1FFF - USB (not all locations used)
0x2000 - 0x201F - DMA controller
0x2020 - 0x202F - UART0
0x2030 - 0x203F - UART1 (IRDA)
0x2040 - the mysterious Program Memory Control bit (???)
0x3000 - 0x37FF - DPRAM
0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
AVR devices did that as well (no need to use LPM!)
*/
#endif /* _AVR_IO76C711_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io8515.h - definitions for AT90S8515 */
#ifndef _AVR_IO8515_H_
#define _AVR_IO8515_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io8515.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter Capture Event */
#define TIMER1_CAPT_vect_num 3
#define TIMER1_CAPT_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 4
#define TIMER1_COMPA_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Compare MatchB */
#define TIMER1_COMPB_vect_num 5
#define TIMER1_COMPB_vect _VECTOR(5)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 6
#define TIMER1_OVF_vect _VECTOR(6)
#define SIG_OVERFLOW1 _VECTOR(6)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 7
#define TIMER0_OVF_vect _VECTOR(7)
#define SIG_OVERFLOW0 _VECTOR(7)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 8
#define SPI_STC_vect _VECTOR(8)
#define SIG_SPI _VECTOR(8)
/* UART, Rx Complete */
#define UART_RX_vect_num 9
#define UART_RX_vect _VECTOR(9)
#define SIG_UART_RECV _VECTOR(9)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 10
#define UART_UDRE_vect _VECTOR(10)
#define SIG_UART_DATA _VECTOR(10)
/* UART, Tx Complete */
#define UART_TX_vect_num 11
#define UART_TX_vect _VECTOR(11)
#define SIG_UART_TRANS _VECTOR(11)
/* Analog Comparator */
#define ANA_COMP_vect_num 12
#define ANA_COMP_vect _VECTOR(12)
#define SIG_COMPARATOR _VECTOR(12)
#define _VECTORS_SIZE 26
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define TICIE1 3
#define TOIE0 1
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define ICF1 3
#define TOV0 1
/* MCU general Control Register */
#define SRE 7
#define SRW 6
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x25F /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x1FF
#define E2PAGESIZE 0
#define FLASHEND 0x1FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */
#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x01
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM)
#endif /* _AVR_IO8515_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io8534.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */
/* avr/io8534.h - definitions for AT90C8534 */
#ifndef _AVR_IO8534_
#define _AVR_IO8534_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io8534.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* 0x00..0x03 reserved */
/* ADC Data Register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and Status Register */
#define ADCSR _SFR_IO8(0x06)
/* ADC Multiplexer Select Register */
#define ADMUX _SFR_IO8(0x07)
/* 0x08..0x0F reserved */
/* General Interrupt Pin Register */
#define GIPR _SFR_IO8(0x10)
/* 0x11..0x19 reserved */
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* 0x20..0x2B reserved */
/* Timer/Counter1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter1 Control Register */
#define TCCR1 _SFR_IO8(0x2E)
/* 0x2F..0x31 reserved */
/* Timer/Counter0 (8-bit) */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* 0x34 reserved */
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* 0x36..0x37 reserved */
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK Register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C reserved */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
#define SIG_INTERRUPT0 _VECTOR(1)
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_OVERFLOW1 _VECTOR(3)
#define SIG_OVERFLOW0 _VECTOR(4)
#define SIG_ADC _VECTOR(5)
#define SIG_EEPROM_READY _VECTOR(6)
#define _VECTORS_SIZE 14
/* Bit numbers */
/* GIMSK */
#define INT1 7
#define INT0 6
/* GIFR */
#define INTF1 7
#define INTF0 6
/* GIPR */
#define IPIN1 3
#define IPIN0 2
/* TIMSK */
#define TOIE1 2
#define TOIE0 0
/* TIFR */
#define TOV1 2
#define TOV0 0
/* MCUCR */
#define SE 6
#define SM 5
#define ISC1 2
#define ISC0 0
/* TCCR0 */
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR1 */
#define CS12 2
#define CS11 1
#define CS10 0
/* PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Last memory addresses */
#define RAMSTART 0x60
#define RAMEND 0x15F
#define XRAMEND RAMEND
#define E2END 0x1FF
#define FLASHEND 0x1FFF
#endif /* _AVR_IO8534_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io8535.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/io8535.h - definitions for AT90S8535 */
#ifndef _AVR_IO8535_H_
#define _AVR_IO8535_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io8535.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* ADC Data register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and Status Register */
#define ADCSR _SFR_IO8(0x06)
/* ADC MUX */
#define ADMUX _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Asynchronous mode Status Register */
#define ASSR _SFR_IO8(0x22)
/* Timer/Counter2 Output Compare Register */
#define OCR2 _SFR_IO8(0x23)
/* Timer/Counter 2 */
#define TCNT2 _SFR_IO8(0x24)
/* Timer/Counter 2 Control Register */
#define TCCR2 _SFR_IO8(0x25)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 3
#define TIMER2_COMP_vect _VECTOR(3)
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 4
#define TIMER2_OVF_vect _VECTOR(4)
#define SIG_OVERFLOW2 _VECTOR(4)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 5
#define TIMER1_CAPT_vect _VECTOR(5)
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 6
#define TIMER1_COMPA_vect _VECTOR(6)
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 7
#define TIMER1_COMPB_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 8
#define TIMER1_OVF_vect _VECTOR(8)
#define SIG_OVERFLOW1 _VECTOR(8)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 9
#define TIMER0_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW0 _VECTOR(9)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 10
#define SPI_STC_vect _VECTOR(10)
#define SIG_SPI _VECTOR(10)
/* UART, RX Complete */
#define UART_RX_vect_num 11
#define UART_RX_vect _VECTOR(11)
#define SIG_UART_RECV _VECTOR(11)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 12
#define UART_UDRE_vect _VECTOR(12)
#define SIG_UART_DATA _VECTOR(12)
/* UART, TX Complete */
#define UART_TX_vect_num 13
#define UART_TX_vect _VECTOR(13)
#define SIG_UART_TRANS _VECTOR(13)
/* ADC Conversion Complete */
#define ADC_vect_num 14
#define ADC_vect _VECTOR(14)
#define SIG_ADC _VECTOR(14)
/* EEPROM Ready */
#define EE_RDY_vect_num 15
#define EE_RDY_vect _VECTOR(15)
#define SIG_EEPROM_READY _VECTOR(15)
/* Analog Comparator */
#define ANA_COMP_vect_num 16
#define ANA_COMP_vect _VECTOR(16)
#define SIG_COMPARATOR _VECTOR(16)
#define _VECTORS_SIZE 34
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* MCU general Status Register */
#define EXTRF 1
#define PORF 0
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
/* Timer/Counter Interrupt MaSK register */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
#define TOIE0 0
/* Timer/Counter Interrupt Flag register */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
#define TOV0 0
/* MCU general Control Register */
#define SE 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter 2 Control Register */
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* Asynchronous mode Status Register */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADC MUX */
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADC Control and Status Register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x25F /*Last On-Chip SRAM location*/
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 0
#define FLASHEND 0x1FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */
#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */
#define LFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x03
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_ADC _BV(SM0)
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
#endif /* _AVR_IO8535_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io86r401.h
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/* Copyright (c) 2002, Colin O'Flynn
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* avr/io86r401.h - definitions for AT86RF401 */
#ifndef _AVR_IO86RF401_H_
#define _AVR_IO86RF401_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io86r401.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#include <avr/sfr_defs.h>
/* Status REGister */
#define SREG _SFR_IO8(0x3F)
/* Stack Pointer */
#define SP _SFR_IO16(0x3D)
#define SPH _SFR_IO8(0x3E)
#define SPL _SFR_IO8(0x3D)
/*Battery low configeration register */
#define BL_CONFIG _SFR_IO8(0x35)
/*Button detect register*/
#define B_DET _SFR_IO8(0x34)
/*AVR Configeration register*/
#define AVR_CONFIG _SFR_IO8(0x33)
/* I/O registers */
/*Data in register */
#define IO_DATIN _SFR_IO8(0x32)
/*Data out register */
#define IO_DATOUT _SFR_IO8(0x31)
/*IO Enable register */
#define IO_ENAB _SFR_IO8(0x30)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x22)
/* Bit Timer Control Register */
#define BTCR _SFR_IO8(0x21)
#define BTCNT _SFR_IO8(0x20)
/*
NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
you may want to remove the leading D.
*/
/* EEPROM Control Register */
/* EEPROM Address Register */
#define DEEAR _SFR_IO8(0x1E)
#define DEEARL _SFR_IO8(0x1E)
/* EEPROM Data Register */
#define DEEDR _SFR_IO8(0x1D)
/* EEPROM Control Register */
#define DEECR _SFR_IO8(0x1C)
/* Lock Detector Configuration Register 2 */
#define LOCKDET2 _SFR_IO8(0x17)
/* VCO Tuning Register*/
#define VCOTUNE _SFR_IO8(0x16)
/* Power Attenuation Control Register */
#define PWR_ATTEN _SFR_IO8(0x14)
/* Transmitter Control Register */
#define TX_CNTL _SFR_IO8(0x12)
/* Lock Detector Configuration Register 1 */
#define LOCKDET1 _SFR_IO8(0x10)
/* Interrupt vectors */
/* Transmission Done, Bit Timer Flag 2 Interrupt */
#define TXDONE_vect_num 1
#define TXDONE_vect _VECTOR(1)
#define SIG_TXDONE _VECTOR(1)
/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */
#define TXEMPTY_vect_num 2
#define TXEMPTY_vect _VECTOR(2)
#define SIG_TXBE _VECTOR(2)
#define _VECTORS_SIZE 12
/*
* The Register Bit names are represented by their bit number (0-7).
*/
/* Lock Detector Configuration Register 1 - LOCKDET1 */
#define UPOK 4
#define ENKO 3
#define BOD 2
#define CS1 1
#define CS0 0
/* Transmit Control Register - TX_CNTL */
#define TXE 5
#define TXK 4
#define LOC 2
/* Power Attenuation Control Register - PWR_ATTEN */
#define PCC2 5
#define PCC1 4
#define PCC0 3
#define PCF2 2
#define PCF1 1
#define PCF0 0
/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/
#define VCOVDET1 7
#define VCOVDET0 6
#define VCOTUNE4 4
#define VCOTUNE3 3
#define VCOTUNE2 2
#define VCOTUNE1 1
#define VCOTUNE0 0
/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/
#define EUD 7
#define LAT 6
#define ULC2 5
#define ULC1 4
#define ULC0 3
#define LC2 2
#define LC1 1
#define LC0 0
/* Data EEPROM Control Register - DEECR */
#define BSY 3
#define EEU 2
#define EEL 1
#define EER 0
/* Data EEPROM Data Register - DEEDR */
#define ED7 7
#define ED6 6
#define ED5 5
#define ED4 4
#define ED3 3
#define ED2 2
#define ED1 1
#define ED0 0
/* Data EEPROM Address Register - DEEAR */
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define BA2 2 /* B is not a typo! */
#define BA1 1
#define BA0 0
/* Bit Timer Count Register - BTCNT */
#define C7 7
#define C6 6
#define C5 5
#define C4 4
#define C3 3
#define C2 2
#define C1 1
#define C0 0
/* Bit Timer Control Register - BTCR */
#define C9 7
#define C8 6
#define M1 5
#define M0 4
#define IE 3
#define F2 2
#define DATA 1
#define F0 0
/* Watchdog Timer Control Register - WDTCR */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* I/O Enable Register - IO_ENAB */
#define BOHYST 6
#define IOE5 5
#define IOE4 4
#define IOE3 3
#define IOE2 2
#define IOE1 1
#define IOE0 0
/* Note: No PORTB or whatever, this is the equivalent. */
/* I/O Data Out Register - IO_DATOUT */
#define IOO5 5
#define IOO4 4
#define IOO3 3
#define IOO2 2
#define IOO1 1
#define IOO0 0
/* Note: No PINB or whatever, this is the equivalent. */
/* I/O Data In Register - IO_DATIN */
#define IOI5 5
#define IOI4 4
#define IOI3 3
#define IOI2 2
#define IOI1 1
#define IOI0 0
/* AVR Configuration Register - AVR_CONFIG */
#define ACS1 6
#define ACS0 5
#define TM 4
#define BD 3
#define BLI 2
#define SLEEP 1
#define BBM 0
/* Button Detect Register - B_DET */
#define BD5 5
#define BD4 4
#define BD3 3
#define BD2 2
#define BD1 1
#define BD0 0
/* Battery Low Configuration Register - BL_CONFIG */
#define BL 7
#define BLV 6
#define BL5 5
#define BL4 4
#define BL3 3
#define BL2 2
#define BL1 1
#define BL0 0
/* Pointer definition */
#define XL r26
#define XH r27
#define YL r28
#define YH r29
#define ZL r30
#define ZH r31
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0xDF
#define XRAMEND RAMEND
#define E2END 0x7F
#define E2PAGESIZE 0
#define FLASHEND 0x07FF
/* Fuses */
#define FUSE_MEMORY_SIZE 0
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x91
#define SIGNATURE_2 0x81
#endif /* _AVR_IO86RF401_H_ */

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arduino/hardware/tools/avr/avr/include/avr/io90pwm161.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_AT90PWM161_H_INCLUDED
#define _AVR_AT90PWM161_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "io90pwm161.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define ACSR _SFR_IO8(0x00)
#define AC1O 1
#define AC2O 2
#define AC3O 3
#define AC1IF 5
#define AC2IF 6
#define AC3IF 7
#define TIMSK1 _SFR_IO8(0x01)
#define TOIE1 0
#define ICIE1 5
#define TIFR1 _SFR_IO8(0x02)
#define TOV1 0
#define ICF1 5
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define ADCSRA _SFR_IO8(0x06)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_IO8(0x07)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ADTS3 3
#define ADSSEN 4
#define ADNCDIS 6
#define ADHSM 7
#define ADMUX _SFR_IO8(0x08)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDRE2 2
// Inserted "DDE2" from "DDRE2" due to compatibility
#define DDE2 2
#define DDRE1 1
// Inserted "DDE1" from "DDRE1" due to compatibility
#define DDE1 1
#define DDRE0 0
// Inserted "DDE0" from "DDRE0" due to compatibility
#define DDE0 0
#define PORTE _SFR_IO8(0x0E)
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
#define PIM0 _SFR_IO8(0x0F)
#define PEOPE0 0
#define PEOEPE0 1
#define PEVE0A 3
#define PEVE0B 4
#define PIFR0 _SFR_IO8(0x10)
#define PEOP0 0
#define PRN00 1
#define PRN01 2
#define PEV0A 3
#define PEV0B 4
#define POAC0A 6
#define POAC0B 7
#define PCNF0 _SFR_IO8(0x11)
#define PCLKSEL0 1
#define POP0 2
#define PMODE00 3
#define PMODE01 4
#define PLOCK0 5
#define PALOCK0 6
#define PFIFTY0 7
#define PCTL0 _SFR_IO8(0x12)
#define PRUN0 0
#define PCCYC0 1
#define PAOC0A 3
#define PAOC0B 4
#define PBFM00 2
#define PBFM01 5
#define PPRE00 6
#define PPRE01 7
#define PIM2 _SFR_IO8(0x13)
#define PEOPE2 0
#define PEOEPE2 1
#define PEVE2A 3
#define PEVE2B 4
#define PSEIE2 5
#define PIFR2 _SFR_IO8(0x14)
#define PEOP2 0
#define PRN20 1
#define PRN21 2
#define PEV2A 3
#define PEV2B 4
#define PSEI2 5
#define POAC2A 6
#define POAC2B 7
#define PCNF2 _SFR_IO8(0x15)
#define POME2 0
#define PCLKSEL2 1
#define POP2 2
#define PMODE20 3
#define PMODE21 4
#define PLOCK2 5
#define PALOCK2 6
#define PFIFTY2 7
#define PCTL2 _SFR_IO8(0x16)
#define PRUN2 0
#define PCCYC2 1
#define PARUN2 2
#define PAOC2A 3
#define PAOC2B 4
#define PBFM2 5
#define PPRE20 6
#define PPRE21 7
#define SPCR _SFR_IO8(0x17)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x18)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define GPIOR0 _SFR_IO8(0x19)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define GPIOR1 _SFR_IO8(0x1A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x1B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define EECR _SFR_IO8(0x1C)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEPAGE 6
#define NVMBSY 7
#define EEDR _SFR_IO8(0x1D)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
#define EIFR _SFR_IO8(0x20)
#define INTF0 0
#define INTF1 1
#define INTF2 2
#define EIMSK _SFR_IO8(0x21)
#define INT0 0
#define INT1 1
#define INT2 2
/* Combine OCR0SBL and OCR0SBH */
#define OCR0SB _SFR_IO16(0x22)
#define OCR0SBL _SFR_IO8(0x22)
#define OCR0SBH _SFR_IO8(0x23)
/* Combine OCR0RBL and OCR0RBH */
#define OCR0RB _SFR_IO16(0x24)
#define OCR0RBL _SFR_IO8(0x24)
#define OCR0RBH _SFR_IO8(0x25)
/* Combine OCR2SBL and OCR2SBH */
#define OCR2SB _SFR_IO16(0x26)
#define OCR2SBL _SFR_IO8(0x26)
#define OCR2SBH _SFR_IO8(0x27)
/* Combine OCR2RBL and OCR2RBH */
#define OCR2RB _SFR_IO16(0x28)
#define OCR2RBL _SFR_IO8(0x28)
#define OCR2RBH _SFR_IO8(0x29)
/* Combine OCR0RAL and OCR0RAH */
#define OCR0RA _SFR_IO16(0x2A)
#define OCR0RAL _SFR_IO8(0x2A)
#define OCR0RAH _SFR_IO8(0x2B)
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x2C)
#endif
#define ADCW _SFR_IO16(0x2C)
#define ADCL _SFR_IO8(0x2C)
#define ADCH _SFR_IO8(0x2D)
/* Combine OCR2RAL and OCR2RAH */
#define OCR2RA _SFR_IO16(0x2E)
#define OCR2RAL _SFR_IO8(0x2E)
#define OCR2RAH _SFR_IO8(0x2F)
/* Reserved [0x30..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define CKRC81 2
#define RSTDIS 3
#define PUD 4
#define SPDR _SFR_IO8(0x36)
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define DACL _SFR_IO8(0x38)
#define DACL0 0
#define DACL1 1
#define DACL2 2
#define DACL3 3
#define DACL4 4
#define DACL5 5
#define DACL6 6
#define DACL7 7
#define DACH _SFR_IO8(0x39)
#define DACH0 0
#define DACH1 1
#define DACH2 2
#define DACH3 3
#define DACH4 4
#define DACH5 5
#define DACH6 6
#define DACH7 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_IO16(0x3A)
#define TCNT1L _SFR_IO8(0x3A)
#define TCNT1H _SFR_IO8(0x3B)
/* Reserved [0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
/* Combine OCR0SAL and OCR0SAH */
#define OCR0SA _SFR_MEM16(0x60)
#define OCR0SAL _SFR_MEM8(0x60)
#define OCR0SAH _SFR_MEM8(0x61)
#define PFRC0A _SFR_MEM8(0x62)
#define PRFM0A0 0
#define PRFM0A1 1
#define PRFM0A2 2
#define PRFM0A3 3
#define PFLTE0A 4
#define PELEV0A 5
#define PISEL0A 6
#define PCAE0A 7
#define PFRC0B _SFR_MEM8(0x63)
#define PRFM0B0 0
#define PRFM0B1 1
#define PRFM0B2 2
#define PRFM0B3 3
#define PFLTE0B 4
#define PELEV0B 5
#define PISEL0B 6
#define PCAE0B 7
/* Combine OCR2SAL and OCR2SAH */
#define OCR2SA _SFR_MEM16(0x64)
#define OCR2SAL _SFR_MEM8(0x64)
#define OCR2SAH _SFR_MEM8(0x65)
#define PFRC2A _SFR_MEM8(0x66)
#define PRFM2A0 0
#define PRFM2A1 1
#define PRFM2A2 2
#define PRFM2A3 3
#define PFLTE2A 4
#define PELEV2A 5
#define PISEL2A 6
#define PCAE2A 7
#define PFRC2B _SFR_MEM8(0x67)
#define PRFM2B0 0
#define PRFM2B1 1
#define PRFM2B2 2
#define PRFM2B3 3
#define PFLTE2B 4
#define PELEV2B 5
#define PISEL2B 6
#define PCAE2B 7
/* Combine PICR0L and PICR0H */
#define PICR0 _SFR_MEM16(0x68)
#define PICR0L _SFR_MEM8(0x68)
#define PICR0H _SFR_MEM8(0x69)
#define PSOC0 _SFR_MEM8(0x6A)
#define POEN0A 0
#define POEN0B 2
#define PSYNC00 4
#define PSYNC01 5
#define PISEL0B1 6
#define PISEL0A1 7
/* Reserved [0x6B] */
#define PICR2L _SFR_MEM8(0x6C)
#define PICR2H _SFR_MEM8(0x6D)
#define PICR28 0
#define PICR29 1
#define PICR210 2
#define PICR211 3
#define PCST2 7
#define PSOC2 _SFR_MEM8(0x6E)
#define POEN2A 0
#define POEN2C 1
#define POEN2B 2
#define POEN2D 3
#define PSYNC20 4
#define PSYNC21 5
#define POS22 6
#define POS23 7
#define POM2 _SFR_MEM8(0x6F)
#define POMV2A0 0
#define POMV2A1 1
#define POMV2A2 2
#define POMV2A3 3
#define POMV2B0 4
#define POMV2B1 5
#define POMV2B2 6
#define POMV2B3 7
#define PCNFE2 _SFR_MEM8(0x70)
#define PISEL2B1 0
#define PISEL2A1 1
#define PELEV2B1 2
#define PELEV2A1 3
#define PBFM21 4
#define PASDLK20 5
#define PASDLK21 6
#define PASDLK22 7
#define PASDLY2 _SFR_MEM8(0x71)
/* Reserved [0x72..0x75] */
#define DACON _SFR_MEM8(0x76)
#define DAEN 0
#define DALA 2
#define DATS0 4
#define DATS1 5
#define DATS2 6
#define DAATE 7
#define DIDR0 _SFR_MEM8(0x77)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x78)
#define ADC9D 0
#define ADC10D 1
#define AMP0POSD 2
#define ACMP1MD 3
#define AMP0CSR _SFR_MEM8(0x79)
#define AMP0TS0 0
#define AMP0TS1 1
#define AMP0GS 3
#define AMP0G0 4
#define AMP0G1 5
#define AMP0IS 6
#define AMP0EN 7
#define AC1ECON _SFR_MEM8(0x7A)
#define AC1H0 0
#define AC1H1 1
#define AC1H2 2
#define AC1ICE 3
#define AC1OE 4
#define AC1OI 5
#define AC2ECON _SFR_MEM8(0x7B)
#define AC2H0 0
#define AC2H1 1
#define AC2H2 2
#define AC2OE 4
#define AC2OI 5
#define AC3ECON _SFR_MEM8(0x7C)
#define AC3H0 0
#define AC3H1 1
#define AC3H2 2
#define AC3OE 4
#define AC3OI 5
#define AC1CON _SFR_MEM8(0x7D)
#define AC1M0 0
#define AC1M1 1
#define AC1M2 2
#define AC1IS0 4
#define AC1IS1 5
#define AC1IE 6
#define AC1EN 7
#define AC2CON _SFR_MEM8(0x7E)
#define AC2M0 0
#define AC2M1 1
#define AC2M2 2
#define AC2IS0 4
#define AC2IS1 5
#define AC2IE 6
#define AC2EN 7
#define AC3CON _SFR_MEM8(0x7F)
#define AC3M0 0
#define AC3M1 1
#define AC3M2 2
#define AC3OEA 3
#define AC3IS0 4
#define AC3IS1 5
#define AC3IE 6
#define AC3EN 7
#define BGCRR _SFR_MEM8(0x80)
#define BGCR0 0
#define BGCR1 1
#define BGCR2 2
#define BGCR3 3
#define BGCCR _SFR_MEM8(0x81)
#define BGCC0 0
#define BGCC1 1
#define BGCC2 2
#define BGCC3 3
#define WDTCSR _SFR_MEM8(0x82)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x83)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x84)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x85)
#define CKSEL0 0
#define CKSEL1 1
#define CKSEL2 2
#define CKSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x86)
#define PRADC 0
#define PRSPI 2
#define PRTIM1 4
#define PRPSCR 5
#define PRPSC2 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSCR)|(1<<PRPSC2))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRPSCR
#define __AVR_HAVE_PRR_PRPSC2
#define PLLCSR _SFR_MEM8(0x87)
#define PLOCK 0
#define PLLE 1
#define PLLF0 2
#define PLLF1 3
#define PLLF2 4
#define PLLF3 5
#define OSCCAL _SFR_MEM8(0x88)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
#define EICRA _SFR_MEM8(0x89)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define ISC20 4
#define ISC21 5
#define TCCR1B _SFR_MEM8(0x8A)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM13 4
#define ICES1 6
#define ICNC1 7
/* Reserved [0x8B] */
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x8C)
#define ICR1L _SFR_MEM8(0x8C)
#define ICR1H _SFR_MEM8(0x8D)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* PSC2 Capture Event */
#define PSC2_CAPT_vect _VECTOR(1)
#define PSC2_CAPT_vect_num 1
/* PSC2 End Cycle */
#define PSC2_EC_vect _VECTOR(2)
#define PSC2_EC_vect_num 2
/* PSC2 End Of Enhanced Cycle */
#define PSC2_EEC_vect _VECTOR(3)
#define PSC2_EEC_vect_num 3
/* PSC0 Capture Event */
#define PSC0_CAPT_vect _VECTOR(4)
#define PSC0_CAPT_vect_num 4
/* PSC0 End Cycle */
#define PSC0_EC_vect _VECTOR(5)
#define PSC0_EC_vect_num 5
/* PSC0 End Of Enhanced Cycle */
#define PSC0_EEC_vect _VECTOR(6)
#define PSC0_EEC_vect_num 6
/* Analog Comparator 1 */
#define ANALOG_COMP_1_vect _VECTOR(7)
#define ANALOG_COMP_1_vect_num 7
/* Analog Comparator 2 */
#define ANALOG_COMP_2_vect _VECTOR(8)
#define ANALOG_COMP_2_vect_num 8
/* Analog Comparator 3 */
#define ANALOG_COMP_3_vect _VECTOR(9)
#define ANALOG_COMP_3_vect_num 9
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(10)
#define INT0_vect_num 10
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(11)
#define TIMER1_CAPT_vect_num 11
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(12)
#define TIMER1_OVF_vect_num 12
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(13)
#define ADC_vect_num 13
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(14)
#define INT1_vect_num 14
/* SPI Serial Transfer Complet */
#define SPI_STC_vect _VECTOR(15)
#define SPI_STC_vect_num 15
/* External Interrupt Request 2 */
#define INT2_vect _VECTOR(16)
#define INT2_vect_num 16
/* Watchdog Timeout Interrupt */
#define WDT_vect _VECTOR(17)
#define WDT_vect_num 17
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(18)
#define EE_READY_vect_num 18
/* Store Program Memory Read */
#define SPM_READY_vect _VECTOR(19)
#define SPM_READY_vect_num 19
#define _VECTORS_SIZE 80
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_PSCINRB (unsigned char)~_BV(3)
#define FUSE_PSCRV (unsigned char)~_BV(4)
#define FUSE_PSC0RB (unsigned char)~_BV(5)
#define FUSE_PSC2RBA (unsigned char)~_BV(6)
#define FUSE_PSC2RB (unsigned char)~_BV(7)
#define EFUSE_DEFAULT (FUSE_BODLEVEL1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x8B
#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */

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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5272_H_INCLUDED
#define _AVR_ATA5272_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5272.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDRA7 7
// Inserted "DDA7" from "DDRA7" due to compatibility
#define DDA7 7
#define DDRA6 6
// Inserted "DDA6" from "DDRA6" due to compatibility
#define DDA6 6
#define DDRA5 5
// Inserted "DDA5" from "DDRA5" due to compatibility
#define DDA5 5
#define DDRA4 4
// Inserted "DDA4" from "DDRA4" due to compatibility
#define DDA4 4
#define DDRA3 3
// Inserted "DDA3" from "DDRA3" due to compatibility
#define DDA3 3
#define DDRA2 2
// Inserted "DDA2" from "DDRA2" due to compatibility
#define DDA2 2
#define DDRA1 1
// Inserted "DDA1" from "DDRA1" due to compatibility
#define DDA1 1
#define DDRA0 0
// Inserted "DDA0" from "DDRA0" due to compatibility
#define DDA0 0
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Reserved [0x06..0x11] */
#define PORTCR _SFR_IO8(0x12)
#define PUDA 0
#define PUDB 1
#define BBMA 4
#define BBMB 5
/* Reserved [0x13..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
/* Reserved [0x17..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR1 0
#define PSR0 1
#define TSM 7
/* Reserved [0x24] */
#define TCCR0A _SFR_IO8(0x25)
#define WGM00 0
#define WGM01 1
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x26)
#define CS00 0
#define CS01 1
#define CS02 2
#define FOC0A 7
#define TCNT2 _SFR_IO8(0x27)
#define OCR0A _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACIRS 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4
#define SIGRD 5
#define RWWSB 6
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x62)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x63)
#define CSEL0 0
#define CSEL1 1
#define CSEL2 2
#define CSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3
#define PRSPI 4
#define PRLIN 5
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSI
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRLIN
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
/* Reserved [0x70..0x76] */
#define AMISCR _SFR_MEM8(0x77)
#define XREFEN 1
#define AREFEN 2
#define ISRCEN 0
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define BIN 7
#define ACIR0 4
#define ACIR1 5
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define ADC8D 0
#define ADC9D 1
#define ADC10D 2
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCCR1D _SFR_MEM8(0x83)
#define OC1AU 0
#define OC1AV 1
#define OC1AW 2
#define OC1AX 3
#define OC1BU 4
#define OC1BV 5
#define OC1BW 6
#define OC1BX 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR0BUB 0
#define TCR0AUB 1
#define OCR0AUB 3
#define TCN0UB 4
#define AS0 5
#define EXCLK 6
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
#define USIBR _SFR_MEM8(0xBB)
#define USIPP _SFR_MEM8(0xBC)
/* Reserved [0xBD..0xC7] */
#define LINCR _SFR_MEM8(0xC8)
#define LCMD0 0
#define LCMD1 1
#define LCMD2 2
#define LENA 3
#define LCONF0 4
#define LCONF1 5
#define LIN13 6
#define LSWRES 7
#define LINSIR _SFR_MEM8(0xC9)
#define LRXOK 0
#define LTXOK 1
#define LIDOK 2
#define LERR 3
#define LBUSY 4
#define LIDST0 5
#define LIDST1 6
#define LIDST2 7
#define LINENIR _SFR_MEM8(0xCA)
#define LENRXOK 0
#define LENTXOK 1
#define LENIDOK 2
#define LENERR 3
#define LINERR _SFR_MEM8(0xCB)
#define LBERR 0
#define LCERR 1
#define LPERR 2
#define LSERR 3
#define LFERR 4
#define LOVERR 5
#define LTOERR 6
#define LABORT 7
#define LINBTR _SFR_MEM8(0xCC)
#define LBT0 0
#define LBT1 1
#define LBT2 2
#define LBT3 3
#define LBT4 4
#define LBT5 5
#define LDISR 7
#define LINBRRL _SFR_MEM8(0xCD)
#define LDIV0 0
#define LDIV1 1
#define LDIV2 2
#define LDIV3 3
#define LDIV4 4
#define LDIV5 5
#define LDIV6 6
#define LDIV7 7
#define LINBRRH _SFR_MEM8(0xCE)
#define LDIV8 0
#define LDIV9 1
#define LDIV10 2
#define LDIV11 3
#define LINDLR _SFR_MEM8(0xCF)
#define LRXDL0 0
#define LRXDL1 1
#define LRXDL2 2
#define LRXDL3 3
#define LTXDL0 4
#define LTXDL1 5
#define LTXDL2 6
#define LTXDL3 7
#define LINIDR _SFR_MEM8(0xD0)
#define LID0 0
#define LID1 1
#define LID2 2
#define LID3 3
#define LID4 4
#define LID5 5
#define LP0 6
#define LP1 7
#define LINSEL _SFR_MEM8(0xD1)
#define LINDX0 0
#define LINDX1 1
#define LINDX2 2
#define LAINC 3
#define LINDAT _SFR_MEM8(0xD2)
#define LDATA0 0
#define LDATA1 1
#define LDATA2 2
#define LDATA3 3
#define LDATA4 4
#define LDATA5 5
#define LDATA6 6
#define LDATA7 7
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Watchdog Time-Out Interrupt */
#define WDT_vect _VECTOR(5)
#define WDT_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match 1A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter1 Compare Match 1B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match 0A */
#define TIMER0_COMPA_vect _VECTOR(10)
#define TIMER0_COMPA_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* LIN Transfer Complete */
#define LIN_TC_vect _VECTOR(12)
#define LIN_TC_vect_num 12
/* LIN Error */
#define LIN_ERR_vect _VECTOR(13)
#define LIN_ERR_vect_num 13
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(14)
#define SPI_STC_vect_num 14
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(15)
#define ADC_vect_num 15
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(16)
#define EE_RDY_vect_num 16
/* USI Overflow */
#define USI_OVF_vect _VECTOR(19)
#define USI_OVF_vect_num 19
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(34)
#define ANA_COMP_vect_num 34
/* USI Start */
#define USI_START_vect _VECTOR(36)
#define USI_START_vect_num 36
#define _VECTORS_SIZE 74
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x87
#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa5505.h
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@ -1,803 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5505_H_INCLUDED
#define _AVR_ATA5505_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5505.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDRA7 7
// Inserted "DDA7" from "DDRA7" due to compatibility
#define DDA7 7
#define DDRA6 6
// Inserted "DDA6" from "DDRA6" due to compatibility
#define DDA6 6
#define DDRA5 5
// Inserted "DDA5" from "DDRA5" due to compatibility
#define DDA5 5
#define DDRA4 4
// Inserted "DDA4" from "DDRA4" due to compatibility
#define DDA4 4
#define DDRA3 3
// Inserted "DDA3" from "DDRA3" due to compatibility
#define DDA3 3
#define DDRA2 2
// Inserted "DDA2" from "DDRA2" due to compatibility
#define DDA2 2
#define DDRA1 1
// Inserted "DDA1" from "DDRA1" due to compatibility
#define DDA1 1
#define DDRA0 0
// Inserted "DDA0" from "DDRA0" due to compatibility
#define DDA0 0
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Reserved [0x06..0x11] */
#define PORTCR _SFR_IO8(0x12)
#define PUDA 0
#define PUDB 1
#define BBMA 4
#define BBMB 5
/* Reserved [0x13..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
/* Reserved [0x17..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR1 0
#define PSR0 1
#define TSM 7
/* Reserved [0x24] */
#define TCCR0A _SFR_IO8(0x25)
#define WGM00 0
#define WGM01 1
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x26)
#define CS00 0
#define CS01 1
#define CS02 2
#define FOC0A 7
#define TCNT2 _SFR_IO8(0x27)
#define OCR0A _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACIRS 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4
#define SIGRD 5
#define RWWSB 6
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x62)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x63)
#define CSEL0 0
#define CSEL1 1
#define CSEL2 2
#define CSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3
#define PRSPI 4
#define PRLIN 5
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSI
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRLIN
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
/* Reserved [0x70..0x76] */
#define AMISCR _SFR_MEM8(0x77)
#define XREFEN 1
#define AREFEN 2
#define ISRCEN 0
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define BIN 7
#define ACIR0 4
#define ACIR1 5
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define ADC8D 0
#define ADC9D 1
#define ADC10D 2
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCCR1D _SFR_MEM8(0x83)
#define OC1AU 0
#define OC1AV 1
#define OC1AW 2
#define OC1AX 3
#define OC1BU 4
#define OC1BV 5
#define OC1BW 6
#define OC1BX 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR0BUB 0
#define TCR0AUB 1
#define OCR0AUB 3
#define TCN0UB 4
#define AS0 5
#define EXCLK 6
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
#define USIBR _SFR_MEM8(0xBB)
#define USIPP _SFR_MEM8(0xBC)
/* Reserved [0xBD..0xC7] */
#define LINCR _SFR_MEM8(0xC8)
#define LCMD0 0
#define LCMD1 1
#define LCMD2 2
#define LENA 3
#define LCONF0 4
#define LCONF1 5
#define LIN13 6
#define LSWRES 7
#define LINSIR _SFR_MEM8(0xC9)
#define LRXOK 0
#define LTXOK 1
#define LIDOK 2
#define LERR 3
#define LBUSY 4
#define LIDST0 5
#define LIDST1 6
#define LIDST2 7
#define LINENIR _SFR_MEM8(0xCA)
#define LENRXOK 0
#define LENTXOK 1
#define LENIDOK 2
#define LENERR 3
#define LINERR _SFR_MEM8(0xCB)
#define LBERR 0
#define LCERR 1
#define LPERR 2
#define LSERR 3
#define LFERR 4
#define LOVERR 5
#define LTOERR 6
#define LABORT 7
#define LINBTR _SFR_MEM8(0xCC)
#define LBT0 0
#define LBT1 1
#define LBT2 2
#define LBT3 3
#define LBT4 4
#define LBT5 5
#define LDISR 7
#define LINBRRL _SFR_MEM8(0xCD)
#define LDIV0 0
#define LDIV1 1
#define LDIV2 2
#define LDIV3 3
#define LDIV4 4
#define LDIV5 5
#define LDIV6 6
#define LDIV7 7
#define LINBRRH _SFR_MEM8(0xCE)
#define LDIV8 0
#define LDIV9 1
#define LDIV10 2
#define LDIV11 3
#define LINDLR _SFR_MEM8(0xCF)
#define LRXDL0 0
#define LRXDL1 1
#define LRXDL2 2
#define LRXDL3 3
#define LTXDL0 4
#define LTXDL1 5
#define LTXDL2 6
#define LTXDL3 7
#define LINIDR _SFR_MEM8(0xD0)
#define LID0 0
#define LID1 1
#define LID2 2
#define LID3 3
#define LID4 4
#define LID5 5
#define LP0 6
#define LP1 7
#define LINSEL _SFR_MEM8(0xD1)
#define LINDX0 0
#define LINDX1 1
#define LINDX2 2
#define LAINC 3
#define LINDAT _SFR_MEM8(0xD2)
#define LDATA0 0
#define LDATA1 1
#define LDATA2 2
#define LDATA3 3
#define LDATA4 4
#define LDATA5 5
#define LDATA6 6
#define LDATA7 7
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Watchdog Time-Out Interrupt */
#define WDT_vect _VECTOR(5)
#define WDT_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match 1A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter1 Compare Match 1B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match 0A */
#define TIMER0_COMPA_vect _VECTOR(10)
#define TIMER0_COMPA_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* LIN Transfer Complete */
#define LIN_TC_vect _VECTOR(12)
#define LIN_TC_vect_num 12
/* LIN Error */
#define LIN_ERR_vect _VECTOR(13)
#define LIN_ERR_vect_num 13
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(14)
#define SPI_STC_vect_num 14
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(15)
#define ADC_vect_num 15
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(16)
#define EE_RDY_vect_num 16
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(17)
#define ANA_COMP_vect_num 17
/* USI Start */
#define USI_START_vect _VECTOR(18)
#define USI_START_vect_num 18
/* USI Overflow */
#define USI_OVF_vect _VECTOR(19)
#define USI_OVF_vect_num 19
#define _VECTORS_SIZE 80
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x87
#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa5790.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5790_H_INCLUDED
#define _AVR_ATA5790_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5790.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC7 7
// Inserted "DDC7" from "DDRC7" due to compatibility
#define DDC7 7
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C] */
#define TPCR _SFR_IO8(0x0D)
#define TPMA 0
#define TPMOD 1
#define TPMS0 2
#define TPMS1 3
#define TPMD0 4
#define TPMD1 5
#define TPPSD 6
#define TPD 7
#define TPFR _SFR_IO8(0x0E)
#define TPF 0
#define TPA 1
#define TPGAP 2
#define TPPSW 3
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CO32D 3
#define CCS 4
#define ECINS 5
#define CMONEN 6
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define SXF 1
#define RTCF 2
#define T2CR _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CRM 2
#define T2GRM 3
#define T2TOP 4
#define T2RES 5
#define T2TS 6
#define T2E 7
#define T3CR _SFR_IO8(0x12)
#define T3OTM 0
#define T3CTM 1
#define T3CRM 2
#define T3CPRM 3
#define T3TOP 4
#define T3RES 5
#define T3CPTM 6
#define T3E 7
#define AESCR _SFR_IO8(0x13)
#define AESWK 0
#define AESWD 1
#define AESIM 2
#define AESD 3
#define AESXOR 4
#define AESRES 5
#define AESE 7
#define AESSR _SFR_IO8(0x14)
#define AESRF 0
#define AESERF 7
#define TMIFR _SFR_IO8(0x15)
#define TMRXF 0
#define TMTXF 1
#define TMTCF 2
#define TMRXS 3
#define TMTXS 4
#define VMSR _SFR_IO8(0x16)
#define VMF 0
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define LFFR _SFR_IO8(0x18)
#define LFID0F 0
#define LFID1F 1
#define LFFEF 2
#define LFDBF 3
#define LFRSF 4
#define LFSDF 5
#define LFMDF 6
#define LFCAF 7
#define T0IFR _SFR_IO8(0x19)
#define T0F 0
#define T1IFR _SFR_IO8(0x1A)
#define T1F 0
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COF 1
#define T3ICF 2
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define GPIOR _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EELP 6
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define EEPR _SFR_IO8(0x23)
#define EEAP0 0
#define EEAP1 1
#define EEAP2 2
#define EEAP3 3
#define EECCR _SFR_IO8(0x24)
#define EEL0 0
#define EEL1 1
#define EEL2 2
#define EEL3 3
/* Reserved [0x25] */
#define PCICR _SFR_IO8(0x26)
#define PCIE0 0
#define PCIE1 1
#define EIMSK _SFR_IO8(0x27)
#define INT0 0
#define TMDR _SFR_IO8(0x28)
#define AESDR _SFR_IO8(0x29)
#define AESKR _SFR_IO8(0x2A)
#define AESKR0 0
#define AESKR1 1
#define AESKR2 2
#define AESKR3 3
#define AESKR4 4
#define AESKR5 5
#define AESKR6 6
#define AESKR7 7
#define VMCR _SFR_IO8(0x2B)
#define VMLS0 0
#define VMLS1 1
#define VMLS2 2
#define VMLS3 3
#define VMIM 4
#define VMPS 5
#define BODPD 6
#define BODLS 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define LFCR0 _SFR_IO8(0x2F)
#define LFCE1 0
#define LFCE2 1
#define LFCE3 2
#define LFBRS 3
#define LFRBS 4
#define LFMG 5
#define LFVC0 6
#define LFVC1 7
#define LFCR1 _SFR_IO8(0x30)
#define LFM0 0
#define LFM1 1
#define LFFM0 2
#define LFFM1 3
#define LFRMS 4
#define LFRMSA 5
#define LFQCE 6
#define LFRE 7
/* Reserved [0x31] */
#define LFRDB _SFR_IO8(0x32)
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TPRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFSR _SFR_IO8(0x36)
#define LFES 0
#define LFSD 1
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1IE 2
#define T1CS0 3
#define T1CS1 4
#define T1E 7
#define T0CR _SFR_IO8(0x39)
#define T0PS0 0
#define T0PS1 1
#define T0PS2 2
#define T0IE 3
#define T0PR 4
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define SXIE 1
#define RTCIE 2
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLKPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
/* Reserved [0x61..0x62] */
#define PRR0 _SFR_MEM8(0x63)
#define PRLFR 0
#define PRT1 1
#define PRT2 2
#define PRT3 3
#define PRTM 4
#define PRCU 5
#define PRDS 6
#define PRVM 7
#define __AVR_HAVE_PRR0 ((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
#define __AVR_HAVE_PRR0_PRLFR
#define __AVR_HAVE_PRR0_PRT1
#define __AVR_HAVE_PRR0_PRT2
#define __AVR_HAVE_PRR0_PRT3
#define __AVR_HAVE_PRR0_PRTM
#define __AVR_HAVE_PRR0_PRCU
#define __AVR_HAVE_PRR0_PRDS
#define __AVR_HAVE_PRR0_PRVM
#define PRR1 _SFR_MEM8(0x64)
#define PRCI 0
#define PRSPI 1
#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
#define __AVR_HAVE_PRR1_PRCI
#define __AVR_HAVE_PRR1_PRSPI
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6C] */
#define LDCR _SFR_MEM8(0x6D)
#define LDE 0
#define LDCS0 1
#define LDCS1 2
/* Reserved [0x6E..0x6F] */
#define T2CNT _SFR_MEM8(0x70)
#define T2COR _SFR_MEM8(0x71)
/* Reserved [0x72] */
#define T2MR _SFR_MEM8(0x73)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2PS0 3
#define T2PS1 4
#define T2PS2 5
#define T2D0 6
#define T2D1 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
/* Reserved [0x75] */
#define T3CNT _SFR_MEM8(0x76)
#define T3COR _SFR_MEM8(0x77)
#define T3ICR _SFR_MEM8(0x78)
#define T3MRA _SFR_MEM8(0x79)
#define T3CS0 0
#define T3CS1 1
#define T3SCE 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7A)
#define T3PS0 0
#define T3PS1 1
#define T3PS2 2
#define T3IMR _SFR_MEM8(0x7B)
#define T3OIM 0
#define T3CIM 1
#define T3CPIM 2
/* Reserved [0x7C] */
#define TMCR _SFR_MEM8(0x7D)
#define MI1S0 0
#define MI1S1 1
#define MI2S0 2
#define MI2S1 3
#define MI4S0 4
#define MI4S1 5
#define TMCPOL 6
#define TMSSIE 7
#define TMMR _SFR_MEM8(0x7E)
#define MOS0 0
#define MOS1 1
#define MSCS0 2
#define MSCS1 3
#define MOUTC 4
#define TMMS0 5
#define TMMS1 6
#define TM12S 7
#define TMIMR _SFR_MEM8(0x7F)
#define TMRXIM 0
#define TMTXIM 1
#define TMTCIM 2
/* Reserved [0x80..0x81] */
#define LFIMR _SFR_MEM8(0x82)
#define LFID0IM 0
#define LFID1IM 1
#define LFFEIM 2
#define LFDBIM 3
#define LFRSIM 4
#define LFSDIM 5
#define LFMDIM 6
#define LFCAD _SFR_MEM8(0x83)
#define LFID00 _SFR_MEM8(0x84)
#define LFID01 _SFR_MEM8(0x85)
#define LFID02 _SFR_MEM8(0x86)
#define LFID03 _SFR_MEM8(0x87)
#define LFID10 _SFR_MEM8(0x88)
#define LFID11 _SFR_MEM8(0x89)
#define LFID12 _SFR_MEM8(0x8A)
#define LFID13 _SFR_MEM8(0x8B)
#define LFRD0 _SFR_MEM8(0x8C)
#define LFRD1 _SFR_MEM8(0x8D)
#define LFRD2 _SFR_MEM8(0x8E)
#define LFRD3 _SFR_MEM8(0x8F)
#define LFID0M _SFR_MEM8(0x90)
#define ID0FS0 0
#define ID0FS1 1
#define ID0FS2 2
#define ID0FS3 3
#define ID0FS4 4
#define ID0E 7
#define LFID1M _SFR_MEM8(0x91)
#define ID1FS0 0
#define ID1FS1 1
#define ID1FS2 2
#define ID1FS3 3
#define ID1FS4 4
#define ID1E 7
#define LFRDF _SFR_MEM8(0x92)
#define RDFS0 0
#define RDFS1 1
#define RDFS2 2
#define RDFS3 3
#define RDFS4 4
#define RDFE 7
#define LFRSD1 _SFR_MEM8(0x93)
#define LFRSD2 _SFR_MEM8(0x94)
#define LFRSD3 _SFR_MEM8(0x95)
#define LFCC1 _SFR_MEM8(0x96)
#define LFCC2 _SFR_MEM8(0x97)
#define LFCC3 _SFR_MEM8(0x98)
/* Reserved [0x99..0x9B] */
#define TPIMR _SFR_MEM8(0x9C)
#define TPIM 0
/* Reserved [0x9D] */
#define RTCCR _SFR_MEM8(0x9E)
#define RTCR 0
#define RTCDR _SFR_MEM8(0x9F)
/* Reserved [0xA0..0xA7] */
#define TMMDR _SFR_MEM8(0xA8)
#define TMBDR _SFR_MEM8(0xA9)
#define TMTDR _SFR_MEM8(0xAA)
#define TMSR _SFR_MEM8(0xAB)
/* Reserved [0xAC] */
#define CRCDR _SFR_MEM8(0xAD)
#define CRCCR _SFR_MEM8(0xAE)
#define CRCN0 0
#define CRCN1 1
#define CRCN2 2
#define CRCSEL 3
#define REFLI 4
#define REFLO 5
#define CRCRS 7
#define CRCSR _SFR_MEM8(0xAF)
#define CRCBF 0
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* Transponder Mode Interrupt */
#define TPINT_vect _VECTOR(1)
#define TPINT_vect_num 1
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(2)
#define INT0_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Voltage Monitoring Interrupt */
#define VMINT_vect _VECTOR(5)
#define VMINT_vect_num 5
/* Timer0 Interval Interrupt */
#define T0INT_vect _VECTOR(6)
#define T0INT_vect_num 6
/* LF-Receiver Identifier 0 Interrupt */
#define LFID0INT_vect _VECTOR(7)
#define LFID0INT_vect_num 7
/* LF-Receiver Identifier 1 Interrupt */
#define LFID1INT_vect _VECTOR(8)
#define LFID1INT_vect_num 8
/* LF-Receiver Frame End Interrupt */
#define LFFEINT_vect _VECTOR(9)
#define LFFEINT_vect_num 9
/* LF-Receiver Data Buffer full Interrupt */
#define LFDBINT_vect _VECTOR(10)
#define LFDBINT_vect_num 10
/* Timer/Counter3 Capture Event Interrupt */
#define T3CAPINT_vect _VECTOR(11)
#define T3CAPINT_vect_num 11
/* Timer/Counter3 Compare Match Interrupt */
#define T3COMINT_vect _VECTOR(12)
#define T3COMINT_vect_num 12
/* Timer/Counter3 Overflow Interrupt */
#define T3OVFINT_vect _VECTOR(13)
#define T3OVFINT_vect_num 13
/* Timer/Counter2 Compare Match Interrupt */
#define T2COMINT_vect _VECTOR(14)
#define T2COMINT_vect_num 14
/* Timer/Counter2 Overflow Interrupt */
#define T2OVFINT_vect _VECTOR(15)
#define T2OVFINT_vect_num 15
/* Timer 1 Interval Interrupt */
#define T1INT_vect _VECTOR(16)
#define T1INT_vect_num 16
/* SPI Serial Transfer Complete Interrupt */
#define SPISTC_vect _VECTOR(17)
#define SPISTC_vect_num 17
/* Timer Modulator SSI Receive Buffer Interrupt */
#define TMRXBINT_vect _VECTOR(18)
#define TMRXBINT_vect_num 18
/* Timer Modulator SSI Transmit Buffer Interrupt */
#define TMTXBINT_vect _VECTOR(19)
#define TMTXBINT_vect_num 19
/* Timer Modulator Transmit Complete Interrupt */
#define TMTXCINT_vect _VECTOR(20)
#define TMTXCINT_vect_num 20
/* AES Interrupt */
#define AESINT_vect _VECTOR(21)
#define AESINT_vect_num 21
/* LF-Receiver RSSi measurement Interrupt */
#define LFRSSINT_vect _VECTOR(22)
#define LFRSSINT_vect_num 22
/* LF-Receiver Signal Detect Interrupt */
#define LFSDINT_vect _VECTOR(23)
#define LFSDINT_vect_num 23
/* LF-Receiver Manchester Decoder error Interrupt */
#define LFMDINT_vect _VECTOR(24)
#define LFMDINT_vect_num 24
/* External Input Clock Monitoring Interrupt */
#define EXCMINT_vect _VECTOR(25)
#define EXCMINT_vect_num 25
/* External XTAL Oscillator Break Down Interrupt */
#define EXXMINT_vect _VECTOR(26)
#define EXXMINT_vect_num 26
/* Real Time Clock Interrupt */
#define RTCINT_vect _VECTOR(27)
#define RTCINT_vect_num 27
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(28)
#define EEREADY_vect_num 28
/* Store Program Memory Ready */
#define SPMREADY_vect _VECTOR(29)
#define SPMREADY_vect_num 29
#define _VECTORS_SIZE 120
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 2048
#define E2PAGESIZE 16
#define E2END 0x07FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Fuse Byte */
#define FUSE_EXTCLKEN (unsigned char)~_BV(0)
#define FUSE__32OEN (unsigned char)~_BV(1)
#define FUSE_Reserved (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x61
#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa5790n.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5790N_H_INCLUDED
#define _AVR_ATA5790N_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5790n.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC7 7
// Inserted "DDC7" from "DDRC7" due to compatibility
#define DDC7 7
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define T3CR2 _SFR_IO8(0x0C)
#define T3GRES 0
#define T3C2TM 1
#define T3C2RM 2
#define TPCR _SFR_IO8(0x0D)
#define TPMA 0
#define TPMOD 1
#define TPMS0 2
#define TPMS1 3
#define TPMD0 4
#define TPMD1 5
#define TPPSD 6
#define TPD 7
#define TPFR _SFR_IO8(0x0E)
#define TPF 0
#define TPA 1
#define TPGAP 2
#define TPPSW 3
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CO32D 3
#define CCS 4
#define ECINS 5
#define CMONEN 6
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define SXF 1
#define RTCF 2
#define T2CR _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CRM 2
#define T2GRM 3
#define T2TOP 4
#define T2RES 5
#define T2TS 6
#define T2E 7
#define T3CR _SFR_IO8(0x12)
#define T3OTM 0
#define T3CTM 1
#define T3CRM 2
#define T3CPRM 3
#define T3TOP 4
#define T3RES 5
#define T3CPTM 6
#define T3E 7
#define AESCR _SFR_IO8(0x13)
#define AESWK 0
#define AESWD 1
#define AESIM 2
#define AESD 3
#define AESXOR 4
#define AESRES 5
#define AESE 7
#define AESSR _SFR_IO8(0x14)
#define AESRF 0
#define AESERF 7
#define TMIFR _SFR_IO8(0x15)
#define TMRXF 0
#define TMTXF 1
#define TMTCF 2
#define TMRXS 3
#define TMTXS 4
#define VMSR _SFR_IO8(0x16)
#define VMF 0
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define LFFR _SFR_IO8(0x18)
#define LFID0F 0
#define LFID1F 1
#define LFFEF 2
#define LFDBF 3
#define LFRSF 4
#define LFSDF 5
#define LFMDF 6
#define LFCAF 7
#define T0IFR _SFR_IO8(0x19)
#define T0F 0
#define T1IFR _SFR_IO8(0x1A)
#define T1F 0
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COF 1
#define T3ICF 2
#define T3CO2F 3
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define GPIOR _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EELP 6
#define NVMBSY 7
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define EEPR _SFR_IO8(0x23)
#define EEAP0 0
#define EEAP1 1
#define EEAP2 2
#define EEAP3 3
#define EECCR _SFR_IO8(0x24)
#define EEL0 0
#define EEL1 1
#define EEL2 2
#define EEL3 3
#define EECR2 _SFR_IO8(0x25)
#define EEBRE 0
#define EEPAGE 1
#define PCICR _SFR_IO8(0x26)
#define PCIE0 0
#define PCIE1 1
#define EIMSK _SFR_IO8(0x27)
#define INT0 0
#define TMDR _SFR_IO8(0x28)
#define AESDR _SFR_IO8(0x29)
#define AESKR _SFR_IO8(0x2A)
#define AESKR0 0
#define AESKR1 1
#define AESKR2 2
#define AESKR3 3
#define AESKR4 4
#define AESKR5 5
#define AESKR6 6
#define AESKR7 7
#define VMCR _SFR_IO8(0x2B)
#define VMLS0 0
#define VMLS1 1
#define VMLS2 2
#define VMLS3 3
#define VMIM 4
#define VMPS 5
#define BODPD 6
#define BODLS 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define LFCR0 _SFR_IO8(0x2F)
#define LFCE1 0
#define LFCE2 1
#define LFCE3 2
#define LFBRS 3
#define LFRBS 4
#define LFMG 5
#define LFVC0 6
#define LFVC1 7
#define LFCR1 _SFR_IO8(0x30)
#define LFM0 0
#define LFM1 1
#define LFFM0 2
#define LFFM1 3
#define LFRMS 4
#define LFRMSA 5
#define LFQCE 6
#define LFRE 7
/* Reserved [0x31] */
#define LFRDB _SFR_IO8(0x32)
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TPRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFSR _SFR_IO8(0x36)
#define LFES 0
#define LFSD 1
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1IE 2
#define T1CS0 3
#define T1CS1 4
#define T1E 7
#define T0CR _SFR_IO8(0x39)
#define T0PS0 0
#define T0PS1 1
#define T0PS2 2
#define T0IE 3
#define T0PR 4
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define SXIE 1
#define RTCIE 2
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLKPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
/* Reserved [0x61..0x62] */
#define PRR0 _SFR_MEM8(0x63)
#define PRLFR 0
#define PRT1 1
#define PRT2 2
#define PRT3 3
#define PRTM 4
#define PRCU 5
#define PRDS 6
#define PRVM 7
#define __AVR_HAVE_PRR0 ((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
#define __AVR_HAVE_PRR0_PRLFR
#define __AVR_HAVE_PRR0_PRT1
#define __AVR_HAVE_PRR0_PRT2
#define __AVR_HAVE_PRR0_PRT3
#define __AVR_HAVE_PRR0_PRTM
#define __AVR_HAVE_PRR0_PRCU
#define __AVR_HAVE_PRR0_PRDS
#define __AVR_HAVE_PRR0_PRVM
#define PRR1 _SFR_MEM8(0x64)
#define PRCI 0
#define PRSPI 1
#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
#define __AVR_HAVE_PRR1_PRCI
#define __AVR_HAVE_PRR1_PRSPI
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6C] */
#define LDCR _SFR_MEM8(0x6D)
#define LDE 0
#define LDCS0 1
#define LDCS1 2
/* Reserved [0x6E..0x6F] */
#define T2CNT _SFR_MEM8(0x70)
#define T2COR _SFR_MEM8(0x71)
/* Reserved [0x72] */
#define T2MR _SFR_MEM8(0x73)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2PS0 3
#define T2PS1 4
#define T2PS2 5
#define T2D0 6
#define T2D1 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
#define T3CO2R _SFR_MEM8(0x75)
#define T3CNT _SFR_MEM8(0x76)
#define T3COR _SFR_MEM8(0x77)
#define T3ICR _SFR_MEM8(0x78)
#define T3MRA _SFR_MEM8(0x79)
#define T3CS0 0
#define T3CS1 1
#define T3SCE 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7A)
#define T3PS0 0
#define T3PS1 1
#define T3PS2 2
#define T3IMR _SFR_MEM8(0x7B)
#define T3OIM 0
#define T3CIM 1
#define T3CPIM 2
#define T3C2IM 3
/* Reserved [0x7C] */
#define TMCR _SFR_MEM8(0x7D)
#define MI1S0 0
#define MI1S1 1
#define MI2S0 2
#define MI2S1 3
#define MI4S0 4
#define MI4S1 5
#define TMCPOL 6
#define TMSSIE 7
#define TMMR _SFR_MEM8(0x7E)
#define MOS0 0
#define MOS1 1
#define MSCS0 2
#define MSCS1 3
#define MOUTC 4
#define TMMS0 5
#define TMMS1 6
#define TM12S 7
#define TMIMR _SFR_MEM8(0x7F)
#define TMRXIM 0
#define TMTXIM 1
#define TMTCIM 2
/* Reserved [0x80..0x81] */
#define LFIMR _SFR_MEM8(0x82)
#define LFID0IM 0
#define LFID1IM 1
#define LFFEIM 2
#define LFDBIM 3
#define LFRSIM 4
#define LFSDIM 5
#define LFMDIM 6
#define LFCAD _SFR_MEM8(0x83)
#define LFID00 _SFR_MEM8(0x84)
#define LFID01 _SFR_MEM8(0x85)
#define LFID02 _SFR_MEM8(0x86)
#define LFID03 _SFR_MEM8(0x87)
#define LFID10 _SFR_MEM8(0x88)
#define LFID11 _SFR_MEM8(0x89)
#define LFID12 _SFR_MEM8(0x8A)
#define LFID13 _SFR_MEM8(0x8B)
#define LFRD0 _SFR_MEM8(0x8C)
#define LFRD1 _SFR_MEM8(0x8D)
#define LFRD2 _SFR_MEM8(0x8E)
#define LFRD3 _SFR_MEM8(0x8F)
#define LFID0M _SFR_MEM8(0x90)
#define ID0FS0 0
#define ID0FS1 1
#define ID0FS2 2
#define ID0FS3 3
#define ID0FS4 4
#define ID0E 7
#define LFID1M _SFR_MEM8(0x91)
#define ID1FS0 0
#define ID1FS1 1
#define ID1FS2 2
#define ID1FS3 3
#define ID1FS4 4
#define ID1E 7
#define LFRDF _SFR_MEM8(0x92)
#define RDFS0 0
#define RDFS1 1
#define RDFS2 2
#define RDFS3 3
#define RDFS4 4
#define RDFE 7
#define LFRSD1 _SFR_MEM8(0x93)
#define LFRSD2 _SFR_MEM8(0x94)
#define LFRSD3 _SFR_MEM8(0x95)
#define LFCC1 _SFR_MEM8(0x96)
#define LFCC2 _SFR_MEM8(0x97)
#define LFCC3 _SFR_MEM8(0x98)
#define LFQCR _SFR_MEM8(0x99)
#define LFQCLL 0
/* Reserved [0x9A..0x9B] */
#define TPIMR _SFR_MEM8(0x9C)
#define TPIM 0
/* Reserved [0x9D] */
#define RTCCR _SFR_MEM8(0x9E)
#define RTCR 0
#define RTCDR _SFR_MEM8(0x9F)
/* Reserved [0xA0..0xA7] */
#define TMMDR _SFR_MEM8(0xA8)
#define TMBDR _SFR_MEM8(0xA9)
#define TMTDR _SFR_MEM8(0xAA)
#define TMSR _SFR_MEM8(0xAB)
#define CRCPOL _SFR_MEM8(0xAC)
#define CRCDR _SFR_MEM8(0xAD)
#define CRCCR _SFR_MEM8(0xAE)
#define CRCN0 0
#define CRCN1 1
#define CRCN2 2
#define CRCSEL 3
#define REFLI 4
#define REFLO 5
#define STVAL 6
#define CRCRS 7
#define CRCSR _SFR_MEM8(0xAF)
#define CRCBF 0
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* Transponder Mode Interrupt */
#define TPINT_vect _VECTOR(1)
#define TPINT_vect_num 1
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(2)
#define INT0_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Voltage Monitoring Interrupt */
#define VMINT_vect _VECTOR(5)
#define VMINT_vect_num 5
/* Timer0 Interval Interrupt */
#define T0INT_vect _VECTOR(6)
#define T0INT_vect_num 6
/* LF-Receiver Identifier 0 Interrupt */
#define LFID0INT_vect _VECTOR(7)
#define LFID0INT_vect_num 7
/* LF-Receiver Identifier 1 Interrupt */
#define LFID1INT_vect _VECTOR(8)
#define LFID1INT_vect_num 8
/* LF-Receiver Frame End Interrupt */
#define LFFEINT_vect _VECTOR(9)
#define LFFEINT_vect_num 9
/* LF-Receiver Data Buffer full Interrupt */
#define LFDBINT_vect _VECTOR(10)
#define LFDBINT_vect_num 10
/* Timer/Counter3 Capture Event Interrupt */
#define T3CAPINT_vect _VECTOR(11)
#define T3CAPINT_vect_num 11
/* Timer/Counter3 Compare Match Interrupt */
#define T3COMINT_vect _VECTOR(12)
#define T3COMINT_vect_num 12
/* Timer/Counter3 Overflow Interrupt */
#define T3OVFINT_vect _VECTOR(13)
#define T3OVFINT_vect_num 13
/* Timer/Counter3 Compare Match 2 Interrupt */
#define T3COM2INT_vect _VECTOR(14)
#define T3COM2INT_vect_num 14
/* Timer/Counter2 Compare Match Interrupt */
#define T2COMINT_vect _VECTOR(15)
#define T2COMINT_vect_num 15
/* Timer/Counter2 Overflow Interrupt */
#define T2OVFINT_vect _VECTOR(16)
#define T2OVFINT_vect_num 16
/* Timer 1 Interval Interrupt */
#define T1INT_vect _VECTOR(17)
#define T1INT_vect_num 17
/* SPI Serial Transfer Complete Interrupt */
#define SPISTC_vect _VECTOR(18)
#define SPISTC_vect_num 18
/* Timer Modulator SSI Receive Buffer Interrupt */
#define TMRXBINT_vect _VECTOR(19)
#define TMRXBINT_vect_num 19
/* Timer Modulator SSI Transmit Buffer Interrupt */
#define TMTXBINT_vect _VECTOR(20)
#define TMTXBINT_vect_num 20
/* Timer Modulator Transmit Complete Interrupt */
#define TMTXCINT_vect _VECTOR(21)
#define TMTXCINT_vect_num 21
/* AES Interrupt */
#define AESINT_vect _VECTOR(22)
#define AESINT_vect_num 22
/* LF-Receiver RSSi measurement Interrupt */
#define LFRSSINT_vect _VECTOR(23)
#define LFRSSINT_vect_num 23
/* LF-Receiver Signal Detect Interrupt */
#define LFSDINT_vect _VECTOR(24)
#define LFSDINT_vect_num 24
/* LF-Receiver Manchester Decoder error Interrupt */
#define LFMDINT_vect _VECTOR(25)
#define LFMDINT_vect_num 25
/* External Input Clock Monitoring Interrupt */
#define EXCMINT_vect _VECTOR(26)
#define EXCMINT_vect_num 26
/* External XTAL Oscillator Break Down Interrupt */
#define EXXMINT_vect _VECTOR(27)
#define EXXMINT_vect_num 27
/* Real Time Clock Interrupt */
#define RTCINT_vect _VECTOR(28)
#define RTCINT_vect_num 28
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(29)
#define EEREADY_vect_num 29
/* Store Program Memory Ready */
#define SPMREADY_vect _VECTOR(30)
#define SPMREADY_vect_num 30
#define _VECTORS_SIZE 124
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 2048
#define E2PAGESIZE 16
#define E2END 0x07FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Fuse Byte */
#define FUSE__32OEN (unsigned char)~_BV(1)
#define FUSE_Reserved (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x62
#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa5791.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5791_H_INCLUDED
#define _AVR_ATA5791_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5791.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC7 7
// Inserted "DDC7" from "DDRC7" due to compatibility
#define DDC7 7
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define T3CR2 _SFR_IO8(0x0C)
#define T3GRES 0
#define T3C2TM 1
#define T3C2RM 2
#define TPCR _SFR_IO8(0x0D)
#define TPMA 0
#define TPMOD 1
#define TPMS0 2
#define TPMS1 3
#define TPMD0 4
#define TPMD1 5
#define TPPSD 6
#define TPD 7
#define TPFR _SFR_IO8(0x0E)
#define TPF 0
#define TPA 1
#define TPGAP 2
#define TPPSW 3
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CO32D 3
#define CCS 4
#define ECINS 5
#define CMONEN 6
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define SXF 1
#define RTCF 2
#define T2CR _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CRM 2
#define T2GRM 3
#define T2TOP 4
#define T2RES 5
#define T2TS 6
#define T2E 7
#define T3CR _SFR_IO8(0x12)
#define T3OTM 0
#define T3CTM 1
#define T3CRM 2
#define T3CPRM 3
#define T3TOP 4
#define T3RES 5
#define T3CPTM 6
#define T3E 7
#define AESCR _SFR_IO8(0x13)
#define AESWK 0
#define AESWD 1
#define AESIM 2
#define AESD 3
#define AESXOR 4
#define AESRES 5
#define AESE 7
#define AESSR _SFR_IO8(0x14)
#define AESRF 0
#define AESERF 7
#define TMIFR _SFR_IO8(0x15)
#define TMRXF 0
#define TMTXF 1
#define TMTCF 2
#define TMRXS 3
#define TMTXS 4
#define VMSR _SFR_IO8(0x16)
#define VMF 0
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define LFFR _SFR_IO8(0x18)
#define LFID0F 0
#define LFID1F 1
#define LFFEF 2
#define LFDBF 3
#define LFRSF 4
#define LFSDF 5
#define LFMDF 6
#define LFCAF 7
#define T0IFR _SFR_IO8(0x19)
#define T0F 0
#define T1IFR _SFR_IO8(0x1A)
#define T1F 0
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COF 1
#define T3ICF 2
#define T3CO2F 3
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define GPIOR _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EELP 6
#define NVMBSY 7
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define EEPR _SFR_IO8(0x23)
#define EEAP0 0
#define EEAP1 1
#define EEAP2 2
#define EEAP3 3
#define EECCR _SFR_IO8(0x24)
#define EEL0 0
#define EEL1 1
#define EEL2 2
#define EEL3 3
#define EECR2 _SFR_IO8(0x25)
#define EEBRE 0
#define EEPAGE 1
#define PCICR _SFR_IO8(0x26)
#define PCIE0 0
#define PCIE1 1
#define EIMSK _SFR_IO8(0x27)
#define INT0 0
#define TMDR _SFR_IO8(0x28)
#define AESDR _SFR_IO8(0x29)
#define AESKR _SFR_IO8(0x2A)
#define AESKR0 0
#define AESKR1 1
#define AESKR2 2
#define AESKR3 3
#define AESKR4 4
#define AESKR5 5
#define AESKR6 6
#define AESKR7 7
#define VMCR _SFR_IO8(0x2B)
#define VMLS0 0
#define VMLS1 1
#define VMLS2 2
#define VMLS3 3
#define VMIM 4
#define VMPS 5
#define BODPD 6
#define BODLS 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define LFCR0 _SFR_IO8(0x2F)
#define LFCE1 0
#define LFCE2 1
#define LFCE3 2
#define LFBRS 3
#define LFRBS 4
#define LFMG 5
#define LFVC0 6
#define LFVC1 7
#define LFCR1 _SFR_IO8(0x30)
#define LFM0 0
#define LFM1 1
#define LFFM0 2
#define LFFM1 3
#define LFRMS 4
#define LFRMSA 5
#define LFQCE 6
#define LFRE 7
/* Reserved [0x31] */
#define LFRDB _SFR_IO8(0x32)
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TPRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFSR _SFR_IO8(0x36)
#define LFES 0
#define LFSD 1
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1IE 2
#define T1CS0 3
#define T1CS1 4
#define T1E 7
#define T0CR _SFR_IO8(0x39)
#define T0PS0 0
#define T0PS1 1
#define T0PS2 2
#define T0IE 3
#define T0PR 4
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define SXIE 1
#define RTCIE 2
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLKPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
/* Reserved [0x61..0x62] */
#define PRR0 _SFR_MEM8(0x63)
#define PRLFR 0
#define PRT1 1
#define PRT2 2
#define PRT3 3
#define PRTM 4
#define PRCU 5
#define PRDS 6
#define PRVM 7
#define __AVR_HAVE_PRR0 ((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
#define __AVR_HAVE_PRR0_PRLFR
#define __AVR_HAVE_PRR0_PRT1
#define __AVR_HAVE_PRR0_PRT2
#define __AVR_HAVE_PRR0_PRT3
#define __AVR_HAVE_PRR0_PRTM
#define __AVR_HAVE_PRR0_PRCU
#define __AVR_HAVE_PRR0_PRDS
#define __AVR_HAVE_PRR0_PRVM
#define PRR1 _SFR_MEM8(0x64)
#define PRCI 0
#define PRSPI 1
#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
#define __AVR_HAVE_PRR1_PRCI
#define __AVR_HAVE_PRR1_PRSPI
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6C] */
#define LDCR _SFR_MEM8(0x6D)
#define LDE 0
#define LDCS0 1
#define LDCS1 2
/* Reserved [0x6E..0x6F] */
#define T2CNT _SFR_MEM8(0x70)
#define T2COR _SFR_MEM8(0x71)
/* Reserved [0x72] */
#define T2MR _SFR_MEM8(0x73)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2PS0 3
#define T2PS1 4
#define T2PS2 5
#define T2D0 6
#define T2D1 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
#define T3CO2R _SFR_MEM8(0x75)
#define T3CNT _SFR_MEM8(0x76)
#define T3COR _SFR_MEM8(0x77)
#define T3ICR _SFR_MEM8(0x78)
#define T3MRA _SFR_MEM8(0x79)
#define T3CS0 0
#define T3CS1 1
#define T3SCE 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7A)
#define T3PS0 0
#define T3PS1 1
#define T3PS2 2
#define T3IMR _SFR_MEM8(0x7B)
#define T3OIM 0
#define T3CIM 1
#define T3CPIM 2
#define T3C2IM 3
/* Reserved [0x7C] */
#define TMCR _SFR_MEM8(0x7D)
#define MI1S0 0
#define MI1S1 1
#define MI2S0 2
#define MI2S1 3
#define MI4S0 4
#define MI4S1 5
#define TMCPOL 6
#define TMSSIE 7
#define TMMR _SFR_MEM8(0x7E)
#define MOS0 0
#define MOS1 1
#define MSCS0 2
#define MSCS1 3
#define MOUTC 4
#define TMMS0 5
#define TMMS1 6
#define TM12S 7
#define TMIMR _SFR_MEM8(0x7F)
#define TMRXIM 0
#define TMTXIM 1
#define TMTCIM 2
/* Reserved [0x80..0x81] */
#define LFIMR _SFR_MEM8(0x82)
#define LFID0IM 0
#define LFID1IM 1
#define LFFEIM 2
#define LFDBIM 3
#define LFRSIM 4
#define LFSDIM 5
#define LFMDIM 6
#define LFCAD _SFR_MEM8(0x83)
#define LFID00 _SFR_MEM8(0x84)
#define LFID01 _SFR_MEM8(0x85)
#define LFID02 _SFR_MEM8(0x86)
#define LFID03 _SFR_MEM8(0x87)
#define LFID10 _SFR_MEM8(0x88)
#define LFID11 _SFR_MEM8(0x89)
#define LFID12 _SFR_MEM8(0x8A)
#define LFID13 _SFR_MEM8(0x8B)
#define LFRD0 _SFR_MEM8(0x8C)
#define LFRD1 _SFR_MEM8(0x8D)
#define LFRD2 _SFR_MEM8(0x8E)
#define LFRD3 _SFR_MEM8(0x8F)
#define LFID0M _SFR_MEM8(0x90)
#define ID0FS0 0
#define ID0FS1 1
#define ID0FS2 2
#define ID0FS3 3
#define ID0FS4 4
#define ID0E 7
#define LFID1M _SFR_MEM8(0x91)
#define ID1FS0 0
#define ID1FS1 1
#define ID1FS2 2
#define ID1FS3 3
#define ID1FS4 4
#define ID1E 7
#define LFRDF _SFR_MEM8(0x92)
#define RDFS0 0
#define RDFS1 1
#define RDFS2 2
#define RDFS3 3
#define RDFS4 4
#define RDFE 7
#define LFRSD1 _SFR_MEM8(0x93)
#define LFRSD2 _SFR_MEM8(0x94)
#define LFRSD3 _SFR_MEM8(0x95)
#define LFCC1 _SFR_MEM8(0x96)
#define LFCC2 _SFR_MEM8(0x97)
#define LFCC3 _SFR_MEM8(0x98)
#define LFQCR _SFR_MEM8(0x99)
#define LFQCLL 0
/* Reserved [0x9A..0x9B] */
#define TPIMR _SFR_MEM8(0x9C)
#define TPIM 0
/* Reserved [0x9D] */
#define RTCCR _SFR_MEM8(0x9E)
#define RTCR 0
#define RTCDR _SFR_MEM8(0x9F)
/* Reserved [0xA0..0xA7] */
#define TMMDR _SFR_MEM8(0xA8)
#define TMBDR _SFR_MEM8(0xA9)
#define TMTDR _SFR_MEM8(0xAA)
#define TMSR _SFR_MEM8(0xAB)
#define CRCPOL _SFR_MEM8(0xAC)
#define CRCDR _SFR_MEM8(0xAD)
#define CRCCR _SFR_MEM8(0xAE)
#define CRCN0 0
#define CRCN1 1
#define CRCN2 2
#define CRCSEL 3
#define REFLI 4
#define REFLO 5
#define STVAL 6
#define CRCRS 7
#define CRCSR _SFR_MEM8(0xAF)
#define CRCBF 0
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* Transponder Mode Interrupt */
#define TPINT_vect _VECTOR(1)
#define TPINT_vect_num 1
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(2)
#define INT0_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Voltage Monitoring Interrupt */
#define VMINT_vect _VECTOR(5)
#define VMINT_vect_num 5
/* Timer0 Interval Interrupt */
#define T0INT_vect _VECTOR(6)
#define T0INT_vect_num 6
/* LF-Receiver Identifier 0 Interrupt */
#define LFID0INT_vect _VECTOR(7)
#define LFID0INT_vect_num 7
/* LF-Receiver Identifier 1 Interrupt */
#define LFID1INT_vect _VECTOR(8)
#define LFID1INT_vect_num 8
/* LF-Receiver Frame End Interrupt */
#define LFFEINT_vect _VECTOR(9)
#define LFFEINT_vect_num 9
/* LF-Receiver Data Buffer full Interrupt */
#define LFDBINT_vect _VECTOR(10)
#define LFDBINT_vect_num 10
/* Timer/Counter3 Capture Event Interrupt */
#define T3CAPINT_vect _VECTOR(11)
#define T3CAPINT_vect_num 11
/* Timer/Counter3 Compare Match Interrupt */
#define T3COMINT_vect _VECTOR(12)
#define T3COMINT_vect_num 12
/* Timer/Counter3 Overflow Interrupt */
#define T3OVFINT_vect _VECTOR(13)
#define T3OVFINT_vect_num 13
/* Timer/Counter3 Compare Match 2 Interrupt */
#define T3COM2INT_vect _VECTOR(14)
#define T3COM2INT_vect_num 14
/* Timer/Counter2 Compare Match Interrupt */
#define T2COMINT_vect _VECTOR(15)
#define T2COMINT_vect_num 15
/* Timer/Counter2 Overflow Interrupt */
#define T2OVFINT_vect _VECTOR(16)
#define T2OVFINT_vect_num 16
/* Timer 1 Interval Interrupt */
#define T1INT_vect _VECTOR(17)
#define T1INT_vect_num 17
/* SPI Serial Transfer Complete Interrupt */
#define SPISTC_vect _VECTOR(18)
#define SPISTC_vect_num 18
/* Timer Modulator SSI Receive Buffer Interrupt */
#define TMRXBINT_vect _VECTOR(19)
#define TMRXBINT_vect_num 19
/* Timer Modulator SSI Transmit Buffer Interrupt */
#define TMTXBINT_vect _VECTOR(20)
#define TMTXBINT_vect_num 20
/* Timer Modulator Transmit Complete Interrupt */
#define TMTXCINT_vect _VECTOR(21)
#define TMTXCINT_vect_num 21
/* AES Interrupt */
#define AESINT_vect _VECTOR(22)
#define AESINT_vect_num 22
/* LF-Receiver RSSi measurement Interrupt */
#define LFRSSINT_vect _VECTOR(23)
#define LFRSSINT_vect_num 23
/* LF-Receiver Signal Detect Interrupt */
#define LFSDINT_vect _VECTOR(24)
#define LFSDINT_vect_num 24
/* LF-Receiver Manchester Decoder error Interrupt */
#define LFMDINT_vect _VECTOR(25)
#define LFMDINT_vect_num 25
/* External Input Clock Monitoring Interrupt */
#define EXCMINT_vect _VECTOR(26)
#define EXCMINT_vect_num 26
/* External XTAL Oscillator Break Down Interrupt */
#define EXXMINT_vect _VECTOR(27)
#define EXXMINT_vect_num 27
/* Real Time Clock Interrupt */
#define RTCINT_vect _VECTOR(28)
#define RTCINT_vect_num 28
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(29)
#define EEREADY_vect_num 29
/* Store Program Memory Ready */
#define SPMREADY_vect _VECTOR(30)
#define SPMREADY_vect_num 30
#define _VECTORS_SIZE 124
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 2048
#define E2PAGESIZE 16
#define E2END 0x07FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Fuse Byte */
#define FUSE_EXTCLKEN (unsigned char)~_BV(0)
#define FUSE__32OEN (unsigned char)~_BV(1)
#define FUSE_Reserved (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x62
#endif /* #ifdef _AVR_ATA5791_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa5795.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA5795_H_INCLUDED
#define _AVR_ATA5795_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa5795.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C] */
#define TPCR _SFR_IO8(0x0D)
#define TPMA 0
#define TPMOD 1
#define TPMS0 2
#define TPMS1 3
#define TPMD0 4
#define TPMD1 5
#define TPPSD 6
#define TPD 7
#define TPFR _SFR_IO8(0x0E)
#define TPF 0
#define TPA 1
#define TPGAP 2
#define TPPSW 3
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CO32D 3
#define CCS 4
#define ECINS 5
#define CMONEN 6
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define SXF 1
#define RTCF 2
#define T2CR _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CRM 2
#define T2GRM 3
#define T2TOP 4
#define T2RES 5
#define T2TS 6
#define T2E 7
#define T3CR _SFR_IO8(0x12)
#define T3OTM 0
#define T3CTM 1
#define T3CRM 2
#define T3CPRM 3
#define T3TOP 4
#define T3RES 5
#define T3CPTM 6
#define T3E 7
#define AESCR _SFR_IO8(0x13)
#define AESWK 0
#define AESWD 1
#define AESIM 2
#define AESD 3
#define AESXOR 4
#define AESRES 5
#define AESE 7
#define AESSR _SFR_IO8(0x14)
#define AESRF 0
#define AESERF 7
#define TMIFR _SFR_IO8(0x15)
#define TMRXF 0
#define TMTXF 1
#define TMTCF 2
#define TMRXS 3
#define TMTXS 4
#define VMSR _SFR_IO8(0x16)
#define VMF 0
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
/* Reserved [0x18] */
#define T0IFR _SFR_IO8(0x19)
#define T0F 0
#define T1IFR _SFR_IO8(0x1A)
#define T1F 0
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COF 1
#define T3ICF 2
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EELP 6
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define EEPR _SFR_IO8(0x23)
#define EEAP0 0
#define EEAP1 1
#define EEAP2 2
#define EEAP3 3
#define EECCR _SFR_IO8(0x24)
#define EEL0 0
#define EEL1 1
#define EEL2 2
#define EEL3 3
/* Reserved [0x25] */
#define PCICR _SFR_IO8(0x26)
#define PCIE0 0
#define PCIE1 1
#define EIMSK _SFR_IO8(0x27)
#define INT0 0
#define TMDR _SFR_IO8(0x28)
#define AESDR _SFR_IO8(0x29)
#define AESKR _SFR_IO8(0x2A)
#define AESKR0 0
#define AESKR1 1
#define AESKR2 2
#define AESKR3 3
#define AESKR4 4
#define AESKR5 5
#define AESKR6 6
#define AESKR7 7
#define VMCR _SFR_IO8(0x2B)
#define VMLS0 0
#define VMLS1 1
#define VMLS2 2
#define VMLS3 3
#define VMIM 4
#define VMPS 5
#define BODPD 6
#define BODLS 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TPRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1IE 2
#define T1CS0 3
#define T1CS1 4
#define T1E 7
#define T0CR _SFR_IO8(0x39)
#define T0PS0 0
#define T0PS1 1
#define T0PS2 2
#define T0IE 3
#define T0PR 4
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define SXIE 1
#define RTCIE 2
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLKPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
/* Reserved [0x61..0x62] */
#define PRR0 _SFR_MEM8(0x63)
#define PRT1 1
#define PRT2 2
#define PRT3 3
#define PRTM 4
#define PRCU 5
#define PRDS 6
#define PRVM 7
#define __AVR_HAVE_PRR0 ((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
#define __AVR_HAVE_PRR0_PRT1
#define __AVR_HAVE_PRR0_PRT2
#define __AVR_HAVE_PRR0_PRT3
#define __AVR_HAVE_PRR0_PRTM
#define __AVR_HAVE_PRR0_PRCU
#define __AVR_HAVE_PRR0_PRDS
#define __AVR_HAVE_PRR0_PRVM
#define PRR1 _SFR_MEM8(0x64)
#define PRCI 0
#define PRSPI 1
#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
#define __AVR_HAVE_PRR1_PRCI
#define __AVR_HAVE_PRR1_PRSPI
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6C] */
#define LDCR _SFR_MEM8(0x6D)
#define LDE 0
#define LDCS0 1
#define LDCS1 2
/* Reserved [0x6E..0x6F] */
#define T2CNT _SFR_MEM8(0x70)
#define T2COR _SFR_MEM8(0x71)
/* Reserved [0x72] */
#define T2MR _SFR_MEM8(0x73)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2PS0 3
#define T2PS1 4
#define T2PS2 5
#define T2D0 6
#define T2D1 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
/* Reserved [0x75] */
#define T3CNT _SFR_MEM8(0x76)
#define T3COR _SFR_MEM8(0x77)
#define T3ICR _SFR_MEM8(0x78)
#define T3MRA _SFR_MEM8(0x79)
#define T3CS0 0
#define T3CS1 1
#define T3SCE 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7A)
#define T3PS0 0
#define T3PS1 1
#define T3PS2 2
#define T3IMR _SFR_MEM8(0x7B)
#define T3OIM 0
#define T3CIM 1
#define T3CPIM 2
/* Reserved [0x7C] */
#define TMCR _SFR_MEM8(0x7D)
#define MI1S0 0
#define MI1S1 1
#define MI2S0 2
#define MI2S1 3
#define MI4S0 4
#define MI4S1 5
#define TMCPOL 6
#define TMSSIE 7
#define TMMR _SFR_MEM8(0x7E)
#define MOS0 0
#define MOS1 1
#define MSCS0 2
#define MSCS1 3
#define MOUTC 4
#define TMMS0 5
#define TMMS1 6
#define TM12S 7
#define TMIMR _SFR_MEM8(0x7F)
#define TMRXIM 0
#define TMTXIM 1
#define TMTCIM 2
/* Reserved [0x80..0x9B] */
#define TPIMR _SFR_MEM8(0x9C)
#define TPIM 0
/* Reserved [0x9D] */
#define RTCCR _SFR_MEM8(0x9E)
#define RTCR 0
#define RTCDR _SFR_MEM8(0x9F)
/* Reserved [0xA0..0xA7] */
#define TMMDR _SFR_MEM8(0xA8)
#define TMBDR _SFR_MEM8(0xA9)
#define TMTDR _SFR_MEM8(0xAA)
#define TMSR _SFR_MEM8(0xAB)
/* Reserved [0xAC] */
#define CRCDR _SFR_MEM8(0xAD)
#define CRCCR _SFR_MEM8(0xAE)
#define CRCN0 0
#define CRCN1 1
#define CRCN2 2
#define CRCSEL 3
#define REFLI 4
#define REFLO 5
#define CRCRS 7
#define CRCSR _SFR_MEM8(0xAF)
#define CRCBF 0
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* Transponder Mode Interrupt */
#define TPINT_vect _VECTOR(1)
#define TPINT_vect_num 1
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(2)
#define INT0_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Voltage Monitor Interrupt */
#define VMINT_vect _VECTOR(5)
#define VMINT_vect_num 5
/* Timer0 Interval Interrupt */
#define T0INT_vect _VECTOR(6)
#define T0INT_vect_num 6
/* Timer3 Capture Interrupt */
#define T3CAPINT_vect _VECTOR(7)
#define T3CAPINT_vect_num 7
/* Timer3 Compare Match Interrupt */
#define T3COMINT_vect _VECTOR(8)
#define T3COMINT_vect_num 8
/* Timer3 Overflow Interrupt */
#define T3OVFINT_vect _VECTOR(9)
#define T3OVFINT_vect_num 9
/* Timer2 Compare Match Interrupt */
#define T2COMINT_vect _VECTOR(10)
#define T2COMINT_vect_num 10
/* Timer2 Overflow Interrupt */
#define T2OVFINT_vect _VECTOR(11)
#define T2OVFINT_vect_num 11
/* Timer1 Interval Interrupt */
#define T1INT_vect _VECTOR(12)
#define T1INT_vect_num 12
/* SPI Serial Transfer Complete */
#define SPISTC_vect _VECTOR(13)
#define SPISTC_vect_num 13
/* Timer Modulator SSI Receive Buffer Interrupt */
#define TMRXBINT_vect _VECTOR(14)
#define TMRXBINT_vect_num 14
/* Timer Modulator SSI Transmit Buffer Interrupt */
#define TMTXBINT_vect _VECTOR(15)
#define TMTXBINT_vect_num 15
/* Timer Modulator Transmit Complete Interrupt */
#define TMTXCINT_vect _VECTOR(16)
#define TMTXCINT_vect_num 16
/* AES Interrupt */
#define AESINT_vect _VECTOR(17)
#define AESINT_vect_num 17
/* External Input Clock Monitoring Interrupt */
#define EXCMINT_vect _VECTOR(18)
#define EXCMINT_vect_num 18
/* External XTAL Oscillator Break Down Interrupt */
#define EXXMINT_vect _VECTOR(19)
#define EXXMINT_vect_num 19
/* Real Time Clock Interrupt */
#define RTCINT_vect _VECTOR(20)
#define RTCINT_vect_num 20
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(21)
#define EEREADY_vect_num 21
/* Store Program Memory Ready */
#define SPMREADY_vect _VECTOR(22)
#define SPMREADY_vect_num 22
#define _VECTORS_SIZE 46
/* Constants */
#define SPM_PAGESIZE 64
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 2048
#define E2PAGESIZE 16
#define E2END 0x07FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Fuse Byte */
#define FUSE__32OEN (unsigned char)~_BV(1)
#define FUSE_Reserved (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x61
#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6285.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6285_H_INCLUDED
#define _AVR_ATA6285_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6285.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x0E] */
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CMONEN 3
#define CCS 4
#define ECINS 5
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define T2CRA _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CR 2
#define T2CRM 3
#define T2ICS 5
#define T2TS 6
#define T2E 7
#define T2CRB _SFR_IO8(0x12)
#define T2SCE 0
/* Reserved [0x13] */
#define T3CRA _SFR_IO8(0x14)
#define T3AC 0
#define T3SCE 1
#define T3CR 2
#define T3TS 6
#define T3E 7
/* Reserved [0x15] */
#define VMCSR _SFR_IO8(0x16)
#define VMEN 0
#define VMLS0 1
#define VMLS1 2
#define VMLS2 3
#define VMIM 4
#define VMF 5
#define BODPD 6
#define BODLS 7
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define LFFR _SFR_IO8(0x18)
#define LFWPF 0
#define LFBF 1
#define LFEDF 2
#define LFRF 3
#define SSFR _SFR_IO8(0x19)
#define MSENF 0
#define MSENO 1
#define T10IFR _SFR_IO8(0x1A)
#define T0F 0
#define T1F 1
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T2ICF 2
#define T2RXF 3
#define T2TXF 4
#define T2TCF 5
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COAF 1
#define T3COBF 2
#define T3ICF 3
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define INTF1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define PCICR _SFR_IO8(0x23)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EIMSK _SFR_IO8(0x24)
#define INT0 0
#define INT1 1
/* Reserved [0x25..0x26] */
#define SVCR _SFR_IO8(0x27)
#define SCR _SFR_IO8(0x28)
#define SMS 0
#define SEN0 1
#define SEN1 2
#define SMEN 3
#define SCCR _SFR_IO8(0x29)
#define SRCC0 0
#define SRCC1 1
#define SCCS0 2
#define SCCS1 3
#define SCCS2 4
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define T2MDR _SFR_IO8(0x2F)
#define LFRR _SFR_IO8(0x30)
/* Reserved [0x31] */
#define LFCDR _SFR_IO8(0x32)
#define LFDO 0
#define LFRST 6
#define LFSCE 7
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TSRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFRB _SFR_IO8(0x36)
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1PS2 2
#define T1CS0 3
#define T1CS1 4
#define T1CS2 5
#define T1IE 7
#define T0CR _SFR_IO8(0x39)
#define T0PAS0 0
#define T0PAS1 1
#define T0PAS2 2
#define T0IE 3
#define T0PR 4
#define T0PBS0 5
#define T0PBS1 6
#define T0PBS2 7
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
#define SIMSK _SFR_MEM8(0x61)
#define MSIE 0
/* Reserved [0x62..0x63] */
#define TSCR _SFR_MEM8(0x64)
#define TSSD 0
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
#define MSVCAL _SFR_MEM8(0x67)
/* Reserved [0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCMSK2 _SFR_MEM8(0x6C)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
/* Reserved [0x6D] */
#define T2ICRL _SFR_MEM8(0x6E)
#define T2ICR _SFR_MEM8(0x6F)
/* Combine T2CORL and T2CORH */
#define T2COR _SFR_MEM16(0x70)
#define T2CORL _SFR_MEM8(0x70)
#define T2CORH _SFR_MEM8(0x71)
#define T2MRA _SFR_MEM8(0x72)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2CE0 3
#define T2CE1 4
#define T2CNC 5
#define T2TP0 6
#define T2TP1 7
#define T2MRB _SFR_MEM8(0x73)
#define T2M0 0
#define T2M1 1
#define T2M2 2
#define T2M3 3
#define T2TOP 4
#define T2CPOL 6
#define T2SSIE 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
#define T2CPIM 2
#define T2RXIM 3
#define T2TXIM 4
#define T2TCIM 5
/* Reserved [0x75] */
/* Combine T3ICRL and T3ICRH */
#define T3ICR _SFR_MEM16(0x76)
#define T3ICRL _SFR_MEM8(0x76)
#define T3ICRH _SFR_MEM8(0x77)
/* Combine T3CORAL and T3CORAH */
#define T3CORA _SFR_MEM16(0x78)
#define T3CORAL _SFR_MEM8(0x78)
#define T3CORAH _SFR_MEM8(0x79)
/* Combine T3CORBL and T3CORBH */
#define T3CORB _SFR_MEM16(0x7A)
#define T3CORBL _SFR_MEM8(0x7A)
#define T3CORBH _SFR_MEM8(0x7B)
#define T3MRA _SFR_MEM8(0x7C)
#define T3CS0 0
#define T3CS1 1
#define T3CS2 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7D)
#define T3M0 0
#define T3M1 1
#define T3M2 2
#define T3TOP 4
#define T3CRB _SFR_MEM8(0x7E)
#define T3CTMA 0
#define T3SAMA 1
#define T3CRMA 2
#define T3CTMB 3
#define T3SAMB 4
#define T3CRMB 5
#define T3CPRM 6
#define T3IMR _SFR_MEM8(0x7F)
#define T3OIM 0
#define T3CAIM 1
#define T3CBIM 2
#define T3CPIM 3
/* Reserved [0x80] */
#define LFIMR _SFR_MEM8(0x81)
#define LFWIM 0
#define LFBIM 1
#define LFEIM 2
#define LFRCR _SFR_MEM8(0x82)
#define LFEN 0
#define LFBM 1
#define LFWM0 2
#define LFWM1 3
#define LFRSS 4
#define LFCS0 5
#define LFCS1 6
#define LFCS2 7
#define LFHCR _SFR_MEM8(0x83)
/* Combine LFIDCL and LFIDCH */
#define LFIDC _SFR_MEM16(0x84)
#define LFIDCL _SFR_MEM8(0x84)
#define LFIDCH _SFR_MEM8(0x85)
/* Combine LFCALL and LFCALH */
#define LFCAL _SFR_MEM16(0x86)
#define LFCALL _SFR_MEM8(0x86)
#define LFCALH _SFR_MEM8(0x87)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 2 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Voltage Monitor Interrupt */
#define INTVM_vect _VECTOR(6)
#define INTVM_vect_num 6
/* Sensor Interface Interrupt */
#define SENINT_vect _VECTOR(7)
#define SENINT_vect_num 7
/* Timer0 Interval Interrupt */
#define INTT0_vect _VECTOR(8)
#define INTT0_vect_num 8
/* LF-Receiver Wake-up Interrupt */
#define LFWP_vect _VECTOR(9)
#define LFWP_vect_num 9
/* Timer/Counter3 Capture Event */
#define T3CAP_vect _VECTOR(10)
#define T3CAP_vect_num 10
/* Timer/Counter3 Compare Match A */
#define T3COMA_vect _VECTOR(11)
#define T3COMA_vect_num 11
/* Timer/Counter3 Compare Match B */
#define T3COMB_vect _VECTOR(12)
#define T3COMB_vect_num 12
/* Timer/Counter3 Overflow */
#define T3OVF_vect _VECTOR(13)
#define T3OVF_vect_num 13
/* Timer/Counter2 Capture Event */
#define T2CAP_vect _VECTOR(14)
#define T2CAP_vect_num 14
/* Timer/Counter2 Compare Match */
#define T2COM_vect _VECTOR(15)
#define T2COM_vect_num 15
/* Timer/Counter2 Overflow */
#define T2OVF_vect _VECTOR(16)
#define T2OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPISTC_vect _VECTOR(17)
#define SPISTC_vect_num 17
/* LF Receive Buffer Interrupt */
#define LFRXB_vect _VECTOR(18)
#define LFRXB_vect_num 18
/* Timer1 Interval Interrupt */
#define INTT1_vect _VECTOR(19)
#define INTT1_vect_num 19
/* Timer2 SSI Receive Buffer Interrupt */
#define T2RXB_vect _VECTOR(20)
#define T2RXB_vect_num 20
/* Timer2 SSI Transmit Buffer Interrupt */
#define T2TXB_vect _VECTOR(21)
#define T2TXB_vect_num 21
/* Timer2 SSI Transmit Complete Interrupt */
#define T2TXC_vect _VECTOR(22)
#define T2TXC_vect_num 22
/* LF-Receiver End of Burst Interrupt */
#define LFREOB_vect _VECTOR(23)
#define LFREOB_vect_num 23
/* External Input Clock break down Interrupt */
#define EXCM_vect _VECTOR(24)
#define EXCM_vect_num 24
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(25)
#define EEREADY_vect_num 25
/* Store Program Memory Ready */
#define SPM_RDY_vect _VECTOR(26)
#define SPM_RDY_vect_num 26
#define _VECTORS_SIZE 54
/* Constants */
#define SPM_PAGESIZE 64
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 320
#define E2PAGESIZE 4
#define E2END 0x013F
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define FUSE_TSRDI (unsigned char)~_BV(0)
#define FUSE_BODEN (unsigned char)~_BV(1)
#define FUSE_FRCFS (unsigned char)~_BV(2)
#define FUSE_WDRCON (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_EELOCK (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x82
#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6286.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6286_H_INCLUDED
#define _AVR_ATA6286_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6286.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x0E] */
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CMONEN 3
#define CCS 4
#define ECINS 5
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define T2CRA _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CR 2
#define T2CRM 3
#define T2ICS 5
#define T2TS 6
#define T2E 7
#define T2CRB _SFR_IO8(0x12)
#define T2SCE 0
/* Reserved [0x13] */
#define T3CRA _SFR_IO8(0x14)
#define T3AC 0
#define T3SCE 1
#define T3CR 2
#define T3TS 6
#define T3E 7
/* Reserved [0x15] */
#define VMCSR _SFR_IO8(0x16)
#define VMEN 0
#define VMLS0 1
#define VMLS1 2
#define VMLS2 3
#define VMIM 4
#define VMF 5
#define BODPD 6
#define BODLS 7
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define LFFR _SFR_IO8(0x18)
#define LFWPF 0
#define LFBF 1
#define LFEDF 2
#define LFRF 3
#define SSFR _SFR_IO8(0x19)
#define MSENF 0
#define MSENO 1
#define T10IFR _SFR_IO8(0x1A)
#define T0F 0
#define T1F 1
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T2ICF 2
#define T2RXF 3
#define T2TXF 4
#define T2TCF 5
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COAF 1
#define T3COBF 2
#define T3ICF 3
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define INTF1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define PCICR _SFR_IO8(0x23)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EIMSK _SFR_IO8(0x24)
#define INT0 0
#define INT1 1
/* Reserved [0x25..0x26] */
#define SVCR _SFR_IO8(0x27)
#define SCR _SFR_IO8(0x28)
#define SMS 0
#define SEN0 1
#define SEN1 2
#define SMEN 3
#define SCCR _SFR_IO8(0x29)
#define SRCC0 0
#define SRCC1 1
#define SCCS0 2
#define SCCS1 3
#define SCCS2 4
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define T2MDR _SFR_IO8(0x2F)
#define LFRR _SFR_IO8(0x30)
/* Reserved [0x31] */
#define LFCDR _SFR_IO8(0x32)
#define LFDO 0
#define LFRST 6
#define LFSCE 7
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TSRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFRB _SFR_IO8(0x36)
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1PS2 2
#define T1CS0 3
#define T1CS1 4
#define T1CS2 5
#define T1IE 7
#define T0CR _SFR_IO8(0x39)
#define T0PAS0 0
#define T0PAS1 1
#define T0PAS2 2
#define T0IE 3
#define T0PR 4
#define T0PBS0 5
#define T0PBS1 6
#define T0PBS2 7
/* Reserved [0x3A] */
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLPCE 7
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
#define SIMSK _SFR_MEM8(0x61)
#define MSIE 0
/* Reserved [0x62..0x63] */
#define TSCR _SFR_MEM8(0x64)
#define TSSD 0
#define SRCCAL _SFR_MEM8(0x65)
#define FRCCAL _SFR_MEM8(0x66)
#define MSVCAL _SFR_MEM8(0x67)
/* Reserved [0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCMSK2 _SFR_MEM8(0x6C)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
/* Reserved [0x6D] */
#define T2ICRL _SFR_MEM8(0x6E)
#define T2ICR _SFR_MEM8(0x6F)
/* Combine T2CORL and T2CORH */
#define T2COR _SFR_MEM16(0x70)
#define T2CORL _SFR_MEM8(0x70)
#define T2CORH _SFR_MEM8(0x71)
#define T2MRA _SFR_MEM8(0x72)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2CE0 3
#define T2CE1 4
#define T2CNC 5
#define T2TP0 6
#define T2TP1 7
#define T2MRB _SFR_MEM8(0x73)
#define T2M0 0
#define T2M1 1
#define T2M2 2
#define T2M3 3
#define T2TOP 4
#define T2CPOL 6
#define T2SSIE 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
#define T2CPIM 2
#define T2RXIM 3
#define T2TXIM 4
#define T2TCIM 5
/* Reserved [0x75] */
/* Combine T3ICRL and T3ICRH */
#define T3ICR _SFR_MEM16(0x76)
#define T3ICRL _SFR_MEM8(0x76)
#define T3ICRH _SFR_MEM8(0x77)
/* Combine T3CORAL and T3CORAH */
#define T3CORA _SFR_MEM16(0x78)
#define T3CORAL _SFR_MEM8(0x78)
#define T3CORAH _SFR_MEM8(0x79)
/* Combine T3CORBL and T3CORBH */
#define T3CORB _SFR_MEM16(0x7A)
#define T3CORBL _SFR_MEM8(0x7A)
#define T3CORBH _SFR_MEM8(0x7B)
#define T3MRA _SFR_MEM8(0x7C)
#define T3CS0 0
#define T3CS1 1
#define T3CS2 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7D)
#define T3M0 0
#define T3M1 1
#define T3M2 2
#define T3TOP 4
#define T3CRB _SFR_MEM8(0x7E)
#define T3CTMA 0
#define T3SAMA 1
#define T3CRMA 2
#define T3CTMB 3
#define T3SAMB 4
#define T3CRMB 5
#define T3CPRM 6
#define T3IMR _SFR_MEM8(0x7F)
#define T3OIM 0
#define T3CAIM 1
#define T3CBIM 2
#define T3CPIM 3
/* Reserved [0x80] */
#define LFIMR _SFR_MEM8(0x81)
#define LFWIM 0
#define LFBIM 1
#define LFEIM 2
#define LFRCR _SFR_MEM8(0x82)
#define LFEN 0
#define LFBM 1
#define LFWM0 2
#define LFWM1 3
#define LFRSS 4
#define LFCS0 5
#define LFCS1 6
#define LFCS2 7
#define LFHCR _SFR_MEM8(0x83)
/* Combine LFIDCL and LFIDCH */
#define LFIDC _SFR_MEM16(0x84)
#define LFIDCL _SFR_MEM8(0x84)
#define LFIDCH _SFR_MEM8(0x85)
/* Combine LFCALL and LFCALH */
#define LFCAL _SFR_MEM16(0x86)
#define LFCALL _SFR_MEM8(0x86)
#define LFCALH _SFR_MEM8(0x87)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 2 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Voltage Monitor Interrupt */
#define INTVM_vect _VECTOR(6)
#define INTVM_vect_num 6
/* Sensor Interface Interrupt */
#define SENINT_vect _VECTOR(7)
#define SENINT_vect_num 7
/* Timer0 Interval Interrupt */
#define INTT0_vect _VECTOR(8)
#define INTT0_vect_num 8
/* LF-Receiver Wake-up Interrupt */
#define LFWP_vect _VECTOR(9)
#define LFWP_vect_num 9
/* Timer/Counter3 Capture Event */
#define T3CAP_vect _VECTOR(10)
#define T3CAP_vect_num 10
/* Timer/Counter3 Compare Match A */
#define T3COMA_vect _VECTOR(11)
#define T3COMA_vect_num 11
/* Timer/Counter3 Compare Match B */
#define T3COMB_vect _VECTOR(12)
#define T3COMB_vect_num 12
/* Timer/Counter3 Overflow */
#define T3OVF_vect _VECTOR(13)
#define T3OVF_vect_num 13
/* Timer/Counter2 Capture Event */
#define T2CAP_vect _VECTOR(14)
#define T2CAP_vect_num 14
/* Timer/Counter2 Compare Match */
#define T2COM_vect _VECTOR(15)
#define T2COM_vect_num 15
/* Timer/Counter2 Overflow */
#define T2OVF_vect _VECTOR(16)
#define T2OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPISTC_vect _VECTOR(17)
#define SPISTC_vect_num 17
/* LF Receive Buffer Interrupt */
#define LFRXB_vect _VECTOR(18)
#define LFRXB_vect_num 18
/* Timer1 Interval Interrupt */
#define INTT1_vect _VECTOR(19)
#define INTT1_vect_num 19
/* Timer2 SSI Receive Buffer Interrupt */
#define T2RXB_vect _VECTOR(20)
#define T2RXB_vect_num 20
/* Timer2 SSI Transmit Buffer Interrupt */
#define T2TXB_vect _VECTOR(21)
#define T2TXB_vect_num 21
/* Timer2 SSI Transmit Complete Interrupt */
#define T2TXC_vect _VECTOR(22)
#define T2TXC_vect_num 22
/* LF-Receiver End of Burst Interrupt */
#define LFREOB_vect _VECTOR(23)
#define LFREOB_vect_num 23
/* External Input Clock break down Interrupt */
#define EXCM_vect _VECTOR(24)
#define EXCM_vect_num 24
/* EEPROM Ready Interrupt */
#define EEREADY_vect _VECTOR(25)
#define EEREADY_vect_num 25
/* Store Program Memory Ready */
#define SPM_RDY_vect _VECTOR(26)
#define SPM_RDY_vect_num 26
#define _VECTORS_SIZE 54
/* Constants */
#define SPM_PAGESIZE 64
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 320
#define E2PAGESIZE 4
#define E2END 0x013F
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define FUSE_TSRDI (unsigned char)~_BV(0)
#define FUSE_BODEN (unsigned char)~_BV(1)
#define FUSE_FRCFS (unsigned char)~_BV(2)
#define FUSE_WDRCON (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_EELOCK (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x82
#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6289.h
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@ -1,847 +0,0 @@
/* Copyright (c) 2008 Atmel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
/* avr/ioa6289.h - definitions for ATA6289 */
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6289.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#ifndef _AVR_ATA6289_H_
#define _AVR_ATA6289_H_ 1
/* Registers and associated bit numbers. */
#define PINB _SFR_IO8(0x03)
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
#define PINC _SFR_IO8(0x06)
#define PINC0 0
#define PINC1 1
#define DDRC _SFR_IO8(0x07)
#define PORTC _SFR_IO8(0x08)
#define PORTC0 0
#define PORTC1 1
#define PIND _SFR_IO8(0x09)
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7
#define CMCR _SFR_IO8(0x0F)
#define CMM0 0
#define CMM1 1
#define SRCD 2
#define CMONEN 3
#define CCS 4
#define ECINS 5
#define CMCCE 7
#define CMSR _SFR_IO8(0x10)
#define ECF 0
#define T2CRA _SFR_IO8(0x11)
#define T2OTM 0
#define T2CTM 1
#define T2CR 2
#define T2CRM 3
#define T2CPRM 4
#define T2ICS 5
#define T2TS 6
#define T2E 7
#define T2CRB _SFR_IO8(0x12)
#define T2SCE 0
#define T3CRA _SFR_IO8(0x14)
#define T3AC 0
#define T3SCE 1
#define T3CR 2
#define T3TS 6
#define T3E 7
#define VMCSR _SFR_IO8(0x16)
#define VMEN 0
#define VMLS0 1
#define VMLS1 2
#define VMLS2 3
#define VMIM 4
#define VMF 5
#define BODPD 6
#define BODLS 7
#define PCIFR _SFR_IO8(0x17)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define LFFR _SFR_IO8(0x18)
#define LFWPF 0
#define LFBF 1
#define LFEDF 2
#define LFRF 3
#define SSFR _SFR_IO8(0x19)
#define MSENF 0
#define MSENO 1
#define T10IFR _SFR_IO8(0x1A)
#define T0F 0
#define T1F 1
#define T2IFR _SFR_IO8(0x1B)
#define T2OFF 0
#define T2COF 1
#define T2ICF 2
#define T2RXF 3
#define T2TXF 4
#define T2TCF 5
#define T3IFR _SFR_IO8(0x1C)
#define T3OFF 0
#define T3COAF 1
#define T3COBF 2
#define T3ICF 3
#define EIFR _SFR_IO8(0x1D)
#define INTF0 0
#define INTF1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7
#define EEARH _SFR_IO8(0x22)
#define EEAR8 0
#define PCICR _SFR_IO8(0x23)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EIMSK _SFR_IO8(0x24)
#define INT0 0
#define INT1 1
#define SVCR _SFR_IO8(0x27)
#define SVCS0 0
#define SVCS1 1
#define SVCS2 2
#define SVCS3 3
#define SVCS4 4
#define SCR _SFR_IO8(0x28)
#define SMS 0
#define SEN0 1
#define SEN1 2
#define SMEN 3
#define SCCR _SFR_IO8(0x29)
#define SRCC0 0
#define SRCC1 1
#define SCCS0 2
#define SCCS1 3
#define SCCS2 4
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
#define T2MDR _SFR_IO8(0x2F)
#define T2MDR0 0
#define T2MDR1 1
#define T2MDR2 2
#define T2MDR3 3
#define T2MDR4 4
#define T2MDR5 5
#define T2MDR6 6
#define T2MDR7 7
#define LFRR _SFR_IO8(0x30)
#define LFRR0 0
#define LFRR1 1
#define LFRR2 2
#define LFRR3 3
#define LFRR4 4
#define LFRR5 5
#define LFRR6 6
#define LFCDR _SFR_IO8(0x32)
#define LFDO 0
#define LFRST 6
#define LFSCE 7
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define TSRF 5
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define LFRB _SFR_IO8(0x36)
#define LFRB0 0
#define LFRB1 1
#define LFRB2 2
#define LFRB3 3
#define LFRB4 4
#define LFRB5 5
#define LFRB6 6
#define LFRB7 7
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
#define T1CR _SFR_IO8(0x38)
#define T1PS0 0
#define T1PS1 1
#define T1PS2 2
#define T1CS0 3
#define T1CS1 4
#define T1CS2 5
#define T1IE 7
#define T0CR _SFR_IO8(0x39)
#define T0PAS0 0
#define T0PAS1 1
#define T0PAS2 2
#define T0IE 3
#define T0PR 4
#define T0PBS0 5
#define T0PBS1 6
#define T0PBS2 7
#define CMIMR _SFR_IO8(0x3B)
#define ECIE 0
#define CLKPR _SFR_IO8(0x3C)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLTPS0 3
#define CLTPS1 4
#define CLTPS2 5
#define CLPCE 7
#define WDTCR _SFR_MEM8(0x60)
#define WDPS0 0
#define WDPS1 1
#define WDPS2 2
#define WDE 3
#define WDCE 4
#define SIMSK _SFR_MEM8(0x61)
#define MSIE 0
#define TSCR _SFR_MEM8(0x64)
#define TSSD 0
#define SRCCAL _SFR_MEM8(0x65)
#define SCAL0 0
#define SCAL1 1
#define SCAL2 2
#define SCAL3 3
#define SCAL4 4
#define SCAL5 5
#define SCAL6 6
#define SCAL7 7
#define FRCCAL _SFR_MEM8(0x66)
#define FCAL0 0
#define FCAL1 1
#define FCAL2 2
#define FCAL3 3
#define FCAL4 4
#define FCAL5 5
#define FCAL6 6
#define FCAL7 7
#define MSVCAL _SFR_MEM8(0x67)
#define VRCAL0 0
#define VRCAL1 1
#define VRCAL2 2
#define VRCAL3 3
#define VRCAL4 4
#define VRCAL5 5
#define VRCAL6 6
#define VRCAL7 7
#define BGCAL _SFR_MEM8(0x68)
#define BGCAL0 0
#define BGCAL1 1
#define BGCAL2 2
#define BGCAL3 3
#define BGCAL4 4
#define BGCAL5 5
#define BGCAL6 6
#define BGCAL7 7
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define PCMSK0 _SFR_MEM8(0x6A)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6B)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCMSK2 _SFR_MEM8(0x6C)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define T2ICR _SFR_MEM16(0x6E)
#define T2ICRL _SFR_MEM8(0x6E)
#define T2ICRL0 0
#define T2ICRL1 1
#define T2ICRL2 2
#define T2ICRL3 3
#define T2ICRL4 4
#define T2ICRL5 5
#define T2ICRL6 6
#define T2ICRL7 7
#define T2ICRH _SFR_MEM8(0x6F)
#define T2ICRH0 0
#define T2ICRH1 1
#define T2ICRH2 2
#define T2ICRH3 3
#define T2ICRH4 4
#define T2ICRH5 5
#define T2ICRH6 6
#define T2ICRH7 7
#define T2COR _SFR_MEM16(0x70)
#define T2CORL _SFR_MEM8(0x70)
#define T2CORL0 0
#define T2CORL1 1
#define T2CORL2 2
#define T2CORL3 3
#define T2CORL4 4
#define T2CORL5 5
#define T2CORL6 6
#define T2CORL7 7
#define T2CORH _SFR_MEM8(0x71)
#define T2CORH0 0
#define T2CORH1 1
#define T2CORH2 2
#define T2CORH3 3
#define T2CORH4 4
#define T2CORH5 5
#define T2CORH6 6
#define T2CORH7 7
#define T2MRA _SFR_MEM8(0x72)
#define T2CS0 0
#define T2CS1 1
#define T2CS2 2
#define T2CE0 3
#define T2CE1 4
#define T2CNC 5
#define T2TP0 6
#define T2TP1 7
#define T2MRB _SFR_MEM8(0x73)
#define T2M0 0
#define T2M1 1
#define T2M2 2
#define T2M3 3
#define T2TOP 4
#define T2CPOL 6
#define T2SSIE 7
#define T2IMR _SFR_MEM8(0x74)
#define T2OIM 0
#define T2CIM 1
#define T2CPIM 2
#define T2RXIM 3
#define T2TXIM 4
#define T2TCIM 5
#define T3ICR _SFR_MEM16(0x76)
#define T3ICRL _SFR_MEM8(0x76)
#define T3ICRL0 0
#define T3ICRL1 1
#define T3ICRL2 2
#define T3ICRL3 3
#define T3ICRL4 4
#define T3ICRL5 5
#define T3ICRL6 6
#define T3ICRL7 7
#define T3ICRH _SFR_MEM8(0x77)
#define T3ICRH0 0
#define T3ICRH1 1
#define T3ICRH2 2
#define T3ICRH3 3
#define T3ICRH4 4
#define T3ICRH5 5
#define T3ICRH6 6
#define T3ICRH7 7
#define T3CORA _SFR_MEM16(0x78)
#define T3CORAL _SFR_MEM8(0x78)
#define T3CORAL0 0
#define T3CORAL1 1
#define T3CORAL2 2
#define T3CORAL3 3
#define T3CORAL4 4
#define T3CORAL5 5
#define T3CORAL6 6
#define T3CORAL7 7
#define T3CORAH _SFR_MEM8(0x79)
#define T3CORAH0 0
#define T3CORAH1 1
#define T3CORAH2 2
#define T3CORAH3 3
#define T3CORAH4 4
#define T3CORAH5 5
#define T3CORAH6 6
#define T3CORAH7 7
#define T3CORB _SFR_MEM16(0x7A)
#define T3CORBL _SFR_MEM8(0x7A)
#define T3CORBL0 0
#define T3CORBL1 1
#define T3CORBL2 2
#define T3CORBL3 3
#define T3CORBL4 4
#define T3CORBL5 5
#define T3CORBL6 6
#define T3CORBL7 7
#define T3CORBH _SFR_MEM8(0x7B)
#define T3CORBH0 0
#define T3CORBH1 1
#define T3CORBH2 2
#define T3CORBH3 3
#define T3CORBH4 4
#define T3CORBH5 5
#define T3CORBH6 6
#define T3CORBH7 7
#define T3MRA _SFR_MEM8(0x7C)
#define T3CS0 0
#define T3CS1 1
#define T3CS2 2
#define T3CE0 3
#define T3CE1 4
#define T3CNC 5
#define T3ICS0 6
#define T3ICS1 7
#define T3MRB _SFR_MEM8(0x7D)
#define T3M0 0
#define T3M1 1
#define T3M2 2
#define T3TOP 4
#define T3CRB _SFR_MEM8(0x7E)
#define T3CTMA 0
#define T3SAMA 1
#define T3CRMA 2
#define T3CTMB 3
#define T3SAMB 4
#define T3CRMB 5
#define T3CPRM 6
#define T3IMR _SFR_MEM8(0x7F)
#define T3OIM 0
#define T3CAIM 1
#define T3CBIM 2
#define T3CPIM 3
#define LFIMR _SFR_MEM8(0x81)
#define LFWIM 0
#define LFBIM 1
#define LFEIM 2
#define LFRCR _SFR_MEM8(0x82)
#define LFEN 0
#define LFBM 1
#define LFWM0 2
#define LFWM1 3
#define LFRSS 4
#define LFCS0 5
#define LFCS1 6
#define LFCS2 7
#define LFHCR _SFR_MEM8(0x83)
#define LFHCR0 0
#define LFHCR1 1
#define LFHCR2 2
#define LFHCR3 3
#define LFHCR4 4
#define LFHCR5 5
#define LFHCR6 6
#define LFIDC _SFR_MEM16(0x84)
#define LFIDCL _SFR_MEM8(0x84)
#define LFIDCL_0 0
#define LFIDCL_1 1
#define LFIDCL_2 2
#define LFIDCL_3 3
#define LFIDCL_4 4
#define LFIDCL_5 5
#define LFIDCL_6 6
#define LFIDCL_7 7
#define LFIDCH _SFR_MEM8(0x85)
#define LFIDCH_8 0
#define LFIDCH_9 1
#define LFIDCH_10 2
#define LFIDCH_11 3
#define LFIDCH_12 4
#define LFIDCH_13 5
#define LFIDCH_14 6
#define LFIDCH_15 7
#define LFCAL _SFR_MEM16(0x86)
#define LFCALL _SFR_MEM8(0x86)
#define LFCAL_00 0
#define LFCAL_01 1
#define LFCAL_02 2
#define LFCAL_03 3
#define LFCAL_04 4
#define LFCAL_05 5
#define LFCAL_06 6
#define LFCAL_07 7
#define LFCALH _SFR_MEM8(0x87)
#define LFCAL_08 0
#define LFCAL_09 1
#define LFCAL_10 2
#define LFCAL_11 3
#define LFCAL_12 4
#define LFCAL_13 5
#define LFCAL_14 6
#define LFCAL_15 7
/* Interrupt vectors */
/* Vector 0 is the reset vector */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
#define PCINT0_vect_num 3
#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
#define PCINT1_vect_num 4
#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */
#define PCINT2_vect_num 5
#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */
#define INTVM_vect_num 6
#define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */
#define SENINT_vect_num 7
#define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */
#define INTT0_vect_num 8
#define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */
#define LFWP_vect_num 9
#define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */
#define T3CAP_vect_num 10
#define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */
#define T3COMA_vect_num 11
#define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */
#define T3COMB_vect_num 12
#define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */
#define T3OVF_vect_num 13
#define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */
#define T2CAP_vect_num 14
#define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */
#define T2COM_vect_num 15
#define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */
#define T2OVF_vect_num 16
#define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */
#define SPISTC_vect_num 17
#define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
#define LFRXB_vect_num 18
#define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */
#define INTT1_vect_num 19
#define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */
#define T2RXB_vect_num 20
#define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */
#define T2TXB_vect_num 21
#define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */
#define T2TXC_vect_num 22
#define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */
#define LFREOB_vect_num 23
#define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */
#define EXCM_vect_num 24
#define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */
#define EEREADY_vect_num 25
#define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */
#define SPM_RDY_vect_num 26
#define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */
#define _VECTOR_SIZE 2 /* Size of individual vector. */
#define _VECTORS_SIZE (27 * _VECTOR_SIZE)
/* Constants */
#define SPM_PAGESIZE (64)
#define RAMSTART (0x100)
#define RAMSIZE (512)
#define RAMEND (RAMSTART + RAMSIZE - 1)
#define XRAMSTART (NA)
#define XRAMSIZE (0)
#define XRAMEND RAMEND
#define E2END (320 - 1)
#define E2PAGESIZE (4)
#define FLASHEND (8192 - 1)
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */
#define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */
#define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */
#define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */
#define FUSE_SUT0 ~_BV(4) /* Select start-up time */
#define FUSE_SUT1 ~_BV(5) /* Select start-up time */
#define FUSE_CKOUT ~_BV(6) /* Clock output */
#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN)
/* High Fuse Byte */
#define FUSE_BOOTRST ~_BV(0) /* Select reset vector */
#define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */
#define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */
#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */
#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */
#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */
#define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */
#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x82
#define SLEEP_MODE_IDLE (0)
#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
#define SLEEP_MODE_PWR_DOWN (_BV(SM1))
#endif /* _AVR_ATA6289_H_ */

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arduino/hardware/tools/avr/avr/include/avr/ioa6612c.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6612C_H_INCLUDED
#define _AVR_ATA6612C_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6612c.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define PORTC _SFR_IO8(0x08)
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
/* Reserved [0x18..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define TSM 7
#define PSRASY 1
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
#define OCR0B _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
/* Reserved [0x31..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCSR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2B _SFR_MEM8(0xB4)
/* Reserved [0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
/* Reserved [0xB7] */
#define TWBR _SFR_MEM8(0xB8)
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
/* Reserved [0xBE..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCPHA0 1
#define UDORD0 2
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 1 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Watchdog Time-out Interrupt */
#define WDT_vect _VECTOR(6)
#define WDT_vect_num 6
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect _VECTOR(7)
#define TIMER2_COMPA_vect_num 7
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8)
#define TIMER2_COMPB_vect_num 8
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(9)
#define TIMER2_OVF_vect_num 9
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(10)
#define TIMER1_CAPT_vect_num 10
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(11)
#define TIMER1_COMPA_vect_num 11
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 12
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 13
/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(14)
#define TIMER0_COMPA_vect_num 14
/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 15
/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SPI_STC_vect_num 17
/* USART Rx Complete */
#define USART_RX_vect _VECTOR(18)
#define USART_RX_vect_num 18
/* USART, Data Register Empty */
#define USART_UDRE_vect _VECTOR(19)
#define USART_UDRE_vect_num 19
/* USART Tx Complete */
#define USART_TX_vect _VECTOR(20)
#define USART_TX_vect_num 20
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define ADC_vect_num 21
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define EE_READY_vect_num 22
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define ANALOG_COMP_vect_num 23
/* Two-wire Serial Interface */
#define TWI_vect _VECTOR(24)
#define TWI_vect_num 24
/* Store Program Memory Read */
#define SPM_Ready_vect _VECTOR(25)
#define SPM_Ready_vect_num 25
#define _VECTORS_SIZE 52
/* Constants */
#define SPM_PAGESIZE 64
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x0A
#endif /* #ifdef _AVR_ATA6612C_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6613c.h
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@ -1,795 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6613C_H_INCLUDED
#define _AVR_ATA6613C_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6613c.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define PORTC _SFR_IO8(0x08)
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
/* Reserved [0x18..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define TSM 7
#define PSRASY 1
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
#define OCR0B _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
/* Reserved [0x31..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCSR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2B _SFR_MEM8(0xB4)
/* Reserved [0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
/* Reserved [0xB7] */
#define TWBR _SFR_MEM8(0xB8)
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
/* Reserved [0xBE..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCPHA0 1
#define UDORD0 2
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 1 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Watchdog Time-out Interrupt */
#define WDT_vect _VECTOR(6)
#define WDT_vect_num 6
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect _VECTOR(7)
#define TIMER2_COMPA_vect_num 7
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8)
#define TIMER2_COMPB_vect_num 8
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(9)
#define TIMER2_OVF_vect_num 9
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(10)
#define TIMER1_CAPT_vect_num 10
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(11)
#define TIMER1_COMPA_vect_num 11
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 12
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 13
/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(14)
#define TIMER0_COMPA_vect_num 14
/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 15
/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SPI_STC_vect_num 17
/* USART Rx Complete */
#define USART_RX_vect _VECTOR(18)
#define USART_RX_vect_num 18
/* USART, Data Register Empty */
#define USART_UDRE_vect _VECTOR(19)
#define USART_UDRE_vect_num 19
/* USART Tx Complete */
#define USART_TX_vect _VECTOR(20)
#define USART_TX_vect_num 20
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define ADC_vect_num 21
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define EE_READY_vect_num 22
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define ANALOG_COMP_vect_num 23
/* Two-wire Serial Interface */
#define TWI_vect _VECTOR(24)
#define TWI_vect_num 24
/* Store Program Memory Read */
#define SPM_Ready_vect _VECTOR(25)
#define SPM_Ready_vect_num 25
#define _VECTORS_SIZE 104
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x06
#endif /* #ifdef _AVR_ATA6613C_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6614q.h
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@ -1,798 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6614Q_H_INCLUDED
#define _AVR_ATA6614Q_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6614q.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define PORTC _SFR_IO8(0x08)
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
/* Reserved [0x18..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define TSM 7
#define PSRASY 1
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
#define OCR0B _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
/* Reserved [0x31..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCSR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2B _SFR_MEM8(0xB4)
/* Reserved [0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
/* Reserved [0xB7] */
#define TWBR _SFR_MEM8(0xB8)
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
/* Reserved [0xBE..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCPHA0 1
#define UDORD0 2
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 1 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Watchdog Time-out Interrupt */
#define WDT_vect _VECTOR(6)
#define WDT_vect_num 6
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect _VECTOR(7)
#define TIMER2_COMPA_vect_num 7
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8)
#define TIMER2_COMPB_vect_num 8
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(9)
#define TIMER2_OVF_vect_num 9
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(10)
#define TIMER1_CAPT_vect_num 10
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(11)
#define TIMER1_COMPA_vect_num 11
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 12
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 13
/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(14)
#define TIMER0_COMPA_vect_num 14
/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 15
/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SPI_STC_vect_num 17
/* USART Rx Complete */
#define USART_RX_vect _VECTOR(18)
#define USART_RX_vect_num 18
/* USART, Data Register Empty */
#define USART_UDRE_vect _VECTOR(19)
#define USART_UDRE_vect_num 19
/* USART Tx Complete */
#define USART_TX_vect _VECTOR(20)
#define USART_TX_vect_num 20
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define ADC_vect_num 21
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define EE_READY_vect_num 22
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define ANALOG_COMP_vect_num 23
/* Two-wire Serial Interface */
#define TWI_vect _VECTOR(24)
#define TWI_vect_num 24
/* Store Program Memory Read */
#define SPM_Ready_vect _VECTOR(25)
#define SPM_Ready_vect_num 25
#define _VECTORS_SIZE 104
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x7FFF
#define RAMSTART 0x0100
#define RAMSIZE 2048
#define RAMEND 0x08FF
#define E2START 0
#define E2SIZE 1024
#define E2PAGESIZE 4
#define E2END 0x03FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x0F
#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6616c.h
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@ -1,865 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6616C_H_INCLUDED
#define _AVR_ATA6616C_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6616c.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Reserved [0x06..0x11] */
#define PORTCR _SFR_IO8(0x12)
#define PUDA 0
#define PUDB 1
#define BBMA 4
#define BBMB 5
/* Reserved [0x13..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
/* Reserved [0x17..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR1 0
#define PSR0 1
#define TSM 7
/* Reserved [0x24] */
#define TCCR0A _SFR_IO8(0x25)
#define WGM00 0
#define WGM01 1
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x26)
#define CS00 0
#define CS01 1
#define CS02 2
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x27)
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7
#define OCR0A _SFR_IO8(0x28)
#define OCR00 0
#define OCR01 1
#define OCR02 2
#define OCR03 3
#define OCR04 4
#define OCR05 5
#define OCR06 6
#define OCR07 7
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACIRS 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4
#define SIGRD 5
#define RWWSB 6
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x62)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x63)
#define CSEL0 0
#define CSEL1 1
#define CSEL2 2
#define CSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3
#define PRSPI 4
#define PRLIN 5
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSI
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRLIN
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
/* Reserved [0x70..0x76] */
#define AMISCR _SFR_MEM8(0x77)
#define XREFEN 1
#define AREFEN 2
#define ISRCEN 0
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define BIN 7
#define ACIR0 4
#define ACIR1 5
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define ADC8D 4
#define ADC9D 5
#define ADC10D 6
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCCR1D _SFR_MEM8(0x83)
#define OC1AU 0
#define OC1AV 1
#define OC1AW 2
#define OC1AX 3
#define OC1BU 4
#define OC1BV 5
#define OC1BW 6
#define OC1BX 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR0BUB 0
#define TCR0AUB 1
#define OCR0AUB 3
#define TCN0UB 4
#define AS0 5
#define EXCLK 6
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
#define USIDR0 0
#define USIDR1 1
#define USIDR2 2
#define USIDR3 3
#define USIDR4 4
#define USIDR5 5
#define USIDR6 6
#define USIDR7 7
#define USIBR _SFR_MEM8(0xBB)
#define USIBR0 0
#define USIBR1 1
#define USIBR2 2
#define USIBR3 3
#define USIBR4 4
#define USIBR5 5
#define USIBR6 6
#define USIBR7 7
#define USIPP _SFR_MEM8(0xBC)
#define USIPOS 0
/* Reserved [0xBD..0xC7] */
#define LINCR _SFR_MEM8(0xC8)
#define LCMD0 0
#define LCMD1 1
#define LCMD2 2
#define LENA 3
#define LCONF0 4
#define LCONF1 5
#define LIN13 6
#define LSWRES 7
#define LINSIR _SFR_MEM8(0xC9)
#define LRXOK 0
#define LTXOK 1
#define LIDOK 2
#define LERR 3
#define LBUSY 4
#define LIDST0 5
#define LIDST1 6
#define LIDST2 7
#define LINENIR _SFR_MEM8(0xCA)
#define LENRXOK 0
#define LENTXOK 1
#define LENIDOK 2
#define LENERR 3
#define LINERR _SFR_MEM8(0xCB)
#define LBERR 0
#define LCERR 1
#define LPERR 2
#define LSERR 3
#define LFERR 4
#define LOVERR 5
#define LTOERR 6
#define LABORT 7
#define LINBTR _SFR_MEM8(0xCC)
#define LBT0 0
#define LBT1 1
#define LBT2 2
#define LBT3 3
#define LBT4 4
#define LBT5 5
#define LDISR 7
/* Combine LINBRRL and LINBRRH */
#define LINBRR _SFR_MEM16(0xCD)
#define LINBRRL _SFR_MEM8(0xCD)
#define LINBRRH _SFR_MEM8(0xCE)
#define LINBRRL _SFR_MEM8(0xCD)
#define LDIV0 0
#define LDIV1 1
#define LDIV2 2
#define LDIV3 3
#define LDIV4 4
#define LDIV5 5
#define LDIV6 6
#define LDIV7 7
#define LINBRRH _SFR_MEM8(0xCE)
#define LDIV8 0
#define LDIV9 1
#define LDIV10 2
#define LDIV11 3
#define LINDLR _SFR_MEM8(0xCF)
#define LRXDL0 0
#define LRXDL1 1
#define LRXDL2 2
#define LRXDL3 3
#define LTXDL0 4
#define LTXDL1 5
#define LTXDL2 6
#define LTXDL3 7
#define LINIDR _SFR_MEM8(0xD0)
#define LID0 0
#define LID1 1
#define LID2 2
#define LID3 3
#define LID4 4
#define LID5 5
#define LP0 6
#define LP1 7
#define LINSEL _SFR_MEM8(0xD1)
#define LINDX0 0
#define LINDX1 1
#define LINDX2 2
#define LAINC 3
#define LINDAT _SFR_MEM8(0xD2)
#define LDATA0 0
#define LDATA1 1
#define LDATA2 2
#define LDATA3 3
#define LDATA4 4
#define LDATA5 5
#define LDATA6 6
#define LDATA7 7
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Watchdog Time-Out Interrupt */
#define WDT_vect _VECTOR(5)
#define WDT_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match 1A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter1 Compare Match 1B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match 0A */
#define TIMER0_COMPA_vect _VECTOR(10)
#define TIMER0_COMPA_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* LIN Transfer Complete */
#define LIN_TC_vect _VECTOR(12)
#define LIN_TC_vect_num 12
/* LIN Error */
#define LIN_ERR_vect _VECTOR(13)
#define LIN_ERR_vect_num 13
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(14)
#define SPI_STC_vect_num 14
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(15)
#define ADC_vect_num 15
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(16)
#define EE_RDY_vect_num 16
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(17)
#define ANA_COMP_vect_num 17
/* USI Start Condition Detection */
#define USI_START_vect _VECTOR(18)
#define USI_START_vect_num 18
/* USI Counter Overflow */
#define USI_OVF_vect _VECTOR(19)
#define USI_OVF_vect_num 19
#define _VECTORS_SIZE 40
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x1FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x87
#endif /* #ifdef _AVR_ATA6616C_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa6617c.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA6617C_H_INCLUDED
#define _AVR_ATA6617C_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa6617c.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Reserved [0x06..0x11] */
#define PORTCR _SFR_IO8(0x12)
#define PUDA 0
#define PUDB 1
#define BBMA 4
#define BBMB 5
/* Reserved [0x13..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
/* Reserved [0x17..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR1 0
#define PSR0 1
#define TSM 7
/* Reserved [0x24] */
#define TCCR0A _SFR_IO8(0x25)
#define WGM00 0
#define WGM01 1
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x26)
#define CS00 0
#define CS01 1
#define CS02 2
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x27)
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7
#define OCR0A _SFR_IO8(0x28)
#define OCR00 0
#define OCR01 1
#define OCR02 2
#define OCR03 3
#define OCR04 4
#define OCR05 5
#define OCR06 6
#define OCR07 7
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACIRS 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4
#define SIGRD 5
#define RWWSB 6
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x62)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x63)
#define CSEL0 0
#define CSEL1 1
#define CSEL2 2
#define CSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3
#define PRSPI 4
#define PRLIN 5
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSI
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRLIN
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
/* Reserved [0x70..0x76] */
#define AMISCR _SFR_MEM8(0x77)
#define XREFEN 1
#define AREFEN 2
#define ISRCEN 0
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define BIN 7
#define ACIR0 4
#define ACIR1 5
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define ADC8D 4
#define ADC9D 5
#define ADC10D 6
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCCR1D _SFR_MEM8(0x83)
#define OC1AU 0
#define OC1AV 1
#define OC1AW 2
#define OC1AX 3
#define OC1BU 4
#define OC1BV 5
#define OC1BW 6
#define OC1BX 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR0BUB 0
#define TCR0AUB 1
#define OCR0AUB 3
#define TCN0UB 4
#define AS0 5
#define EXCLK 6
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
#define USIDR0 0
#define USIDR1 1
#define USIDR2 2
#define USIDR3 3
#define USIDR4 4
#define USIDR5 5
#define USIDR6 6
#define USIDR7 7
#define USIBR _SFR_MEM8(0xBB)
#define USIBR0 0
#define USIBR1 1
#define USIBR2 2
#define USIBR3 3
#define USIBR4 4
#define USIBR5 5
#define USIBR6 6
#define USIBR7 7
#define USIPP _SFR_MEM8(0xBC)
#define USIPOS 0
/* Reserved [0xBD..0xC7] */
#define LINCR _SFR_MEM8(0xC8)
#define LCMD0 0
#define LCMD1 1
#define LCMD2 2
#define LENA 3
#define LCONF0 4
#define LCONF1 5
#define LIN13 6
#define LSWRES 7
#define LINSIR _SFR_MEM8(0xC9)
#define LRXOK 0
#define LTXOK 1
#define LIDOK 2
#define LERR 3
#define LBUSY 4
#define LIDST0 5
#define LIDST1 6
#define LIDST2 7
#define LINENIR _SFR_MEM8(0xCA)
#define LENRXOK 0
#define LENTXOK 1
#define LENIDOK 2
#define LENERR 3
#define LINERR _SFR_MEM8(0xCB)
#define LBERR 0
#define LCERR 1
#define LPERR 2
#define LSERR 3
#define LFERR 4
#define LOVERR 5
#define LTOERR 6
#define LABORT 7
#define LINBTR _SFR_MEM8(0xCC)
#define LBT0 0
#define LBT1 1
#define LBT2 2
#define LBT3 3
#define LBT4 4
#define LBT5 5
#define LDISR 7
/* Combine LINBRRL and LINBRRH */
#define LINBRR _SFR_MEM16(0xCD)
#define LINBRRL _SFR_MEM8(0xCD)
#define LINBRRH _SFR_MEM8(0xCE)
#define LINBRRL _SFR_MEM8(0xCD)
#define LDIV0 0
#define LDIV1 1
#define LDIV2 2
#define LDIV3 3
#define LDIV4 4
#define LDIV5 5
#define LDIV6 6
#define LDIV7 7
#define LINBRRH _SFR_MEM8(0xCE)
#define LDIV8 0
#define LDIV9 1
#define LDIV10 2
#define LDIV11 3
#define LINDLR _SFR_MEM8(0xCF)
#define LRXDL0 0
#define LRXDL1 1
#define LRXDL2 2
#define LRXDL3 3
#define LTXDL0 4
#define LTXDL1 5
#define LTXDL2 6
#define LTXDL3 7
#define LINIDR _SFR_MEM8(0xD0)
#define LID0 0
#define LID1 1
#define LID2 2
#define LID3 3
#define LID4 4
#define LID5 5
#define LP0 6
#define LP1 7
#define LINSEL _SFR_MEM8(0xD1)
#define LINDX0 0
#define LINDX1 1
#define LINDX2 2
#define LAINC 3
#define LINDAT _SFR_MEM8(0xD2)
#define LDATA0 0
#define LDATA1 1
#define LDATA2 2
#define LDATA3 3
#define LDATA4 4
#define LDATA5 5
#define LDATA6 6
#define LDATA7 7
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Watchdog Time-Out Interrupt */
#define WDT_vect _VECTOR(5)
#define WDT_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match 1A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter1 Compare Match 1B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match 0A */
#define TIMER0_COMPA_vect _VECTOR(10)
#define TIMER0_COMPA_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* LIN Transfer Complete */
#define LIN_TC_vect _VECTOR(12)
#define LIN_TC_vect_num 12
/* LIN Error */
#define LIN_ERR_vect _VECTOR(13)
#define LIN_ERR_vect_num 13
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(14)
#define SPI_STC_vect_num 14
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(15)
#define ADC_vect_num 15
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(16)
#define EE_RDY_vect_num 16
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(17)
#define ANA_COMP_vect_num 17
/* USI Start Condition Detection */
#define USI_START_vect _VECTOR(18)
#define USI_START_vect_num 18
/* USI Counter Overflow */
#define USI_OVF_vect _VECTOR(19)
#define USI_OVF_vect_num 19
#define _VECTORS_SIZE 80
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x87
#endif /* #ifdef _AVR_ATA6617C_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/ioa664251.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATA664251_H_INCLUDED
#define _AVR_ATA664251_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioa664251.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Reserved [0x06..0x11] */
#define PORTCR _SFR_IO8(0x12)
#define PUDA 0
#define PUDB 1
#define BBMA 4
#define BBMB 5
/* Reserved [0x13..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
/* Reserved [0x17..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR1 0
#define PSR0 1
#define TSM 7
/* Reserved [0x24] */
#define TCCR0A _SFR_IO8(0x25)
#define WGM00 0
#define WGM01 1
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x26)
#define CS00 0
#define CS01 1
#define CS02 2
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x27)
#define TCNT00 0
#define TCNT01 1
#define TCNT02 2
#define TCNT03 3
#define TCNT04 4
#define TCNT05 5
#define TCNT06 6
#define TCNT07 7
#define OCR0A _SFR_IO8(0x28)
#define OCR00 0
#define OCR01 1
#define OCR02 2
#define OCR03 3
#define OCR04 4
#define OCR05 5
#define OCR06 6
#define OCR07 7
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACIRS 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define RFLB 3
#define CTPB 4
#define SIGRD 5
#define RWWSB 6
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define CLKCSR _SFR_MEM8(0x62)
#define CLKC0 0
#define CLKC1 1
#define CLKC2 2
#define CLKC3 3
#define CLKRDY 4
#define CLKCCE 7
#define CLKSELR _SFR_MEM8(0x63)
#define CSEL0 0
#define CSEL1 1
#define CSEL2 2
#define CSEL3 3
#define CSUT0 4
#define CSUT1 5
#define COUT 6
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSI 1
#define PRTIM0 2
#define PRTIM1 3
#define PRSPI 4
#define PRLIN 5
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSI
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRLIN
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
/* Reserved [0x70..0x76] */
#define AMISCR _SFR_MEM8(0x77)
#define XREFEN 1
#define AREFEN 2
#define ISRCEN 0
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define BIN 7
#define ACIR0 4
#define ACIR1 5
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define ADC8D 4
#define ADC9D 5
#define ADC10D 6
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCCR1D _SFR_MEM8(0x83)
#define OC1AU 0
#define OC1AV 1
#define OC1AW 2
#define OC1AX 3
#define OC1BU 4
#define OC1BV 5
#define OC1BW 6
#define OC1BX 7
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR0BUB 0
#define TCR0AUB 1
#define OCR0AUB 3
#define TCN0UB 4
#define AS0 5
#define EXCLK 6
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
#define USIDR0 0
#define USIDR1 1
#define USIDR2 2
#define USIDR3 3
#define USIDR4 4
#define USIDR5 5
#define USIDR6 6
#define USIDR7 7
#define USIBR _SFR_MEM8(0xBB)
#define USIBR0 0
#define USIBR1 1
#define USIBR2 2
#define USIBR3 3
#define USIBR4 4
#define USIBR5 5
#define USIBR6 6
#define USIBR7 7
#define USIPP _SFR_MEM8(0xBC)
#define USIPOS 0
/* Reserved [0xBD..0xC7] */
#define LINCR _SFR_MEM8(0xC8)
#define LCMD0 0
#define LCMD1 1
#define LCMD2 2
#define LENA 3
#define LCONF0 4
#define LCONF1 5
#define LIN13 6
#define LSWRES 7
#define LINSIR _SFR_MEM8(0xC9)
#define LRXOK 0
#define LTXOK 1
#define LIDOK 2
#define LERR 3
#define LBUSY 4
#define LIDST0 5
#define LIDST1 6
#define LIDST2 7
#define LINENIR _SFR_MEM8(0xCA)
#define LENRXOK 0
#define LENTXOK 1
#define LENIDOK 2
#define LENERR 3
#define LINERR _SFR_MEM8(0xCB)
#define LBERR 0
#define LCERR 1
#define LPERR 2
#define LSERR 3
#define LFERR 4
#define LOVERR 5
#define LTOERR 6
#define LABORT 7
#define LINBTR _SFR_MEM8(0xCC)
#define LBT0 0
#define LBT1 1
#define LBT2 2
#define LBT3 3
#define LBT4 4
#define LBT5 5
#define LDISR 7
/* Combine LINBRRL and LINBRRH */
#define LINBRR _SFR_MEM16(0xCD)
#define LINBRRL _SFR_MEM8(0xCD)
#define LINBRRH _SFR_MEM8(0xCE)
#define LINBRRL _SFR_MEM8(0xCD)
#define LDIV0 0
#define LDIV1 1
#define LDIV2 2
#define LDIV3 3
#define LDIV4 4
#define LDIV5 5
#define LDIV6 6
#define LDIV7 7
#define LINBRRH _SFR_MEM8(0xCE)
#define LDIV8 0
#define LDIV9 1
#define LDIV10 2
#define LDIV11 3
#define LINDLR _SFR_MEM8(0xCF)
#define LRXDL0 0
#define LRXDL1 1
#define LRXDL2 2
#define LRXDL3 3
#define LTXDL0 4
#define LTXDL1 5
#define LTXDL2 6
#define LTXDL3 7
#define LINIDR _SFR_MEM8(0xD0)
#define LID0 0
#define LID1 1
#define LID2 2
#define LID3 3
#define LID4 4
#define LID5 5
#define LP0 6
#define LP1 7
#define LINSEL _SFR_MEM8(0xD1)
#define LINDX0 0
#define LINDX1 1
#define LINDX2 2
#define LAINC 3
#define LINDAT _SFR_MEM8(0xD2)
#define LDATA0 0
#define LDATA1 1
#define LDATA2 2
#define LDATA3 3
#define LDATA4 4
#define LDATA5 5
#define LDATA6 6
#define LDATA7 7
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Watchdog Time-Out Interrupt */
#define WDT_vect _VECTOR(5)
#define WDT_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match 1A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter1 Compare Match 1B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match 0A */
#define TIMER0_COMPA_vect _VECTOR(10)
#define TIMER0_COMPA_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* LIN Transfer Complete */
#define LIN_TC_vect _VECTOR(12)
#define LIN_TC_vect_num 12
/* LIN Error */
#define LIN_ERR_vect _VECTOR(13)
#define LIN_ERR_vect_num 13
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(14)
#define SPI_STC_vect_num 14
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(15)
#define ADC_vect_num 15
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(16)
#define EE_RDY_vect_num 16
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(17)
#define ANA_COMP_vect_num 17
/* USI Start Condition Detection */
#define USI_START_vect _VECTOR(18)
#define USI_START_vect_num 18
/* USI Counter Overflow */
#define USI_OVF_vect _VECTOR(19)
#define USI_OVF_vect_num 19
#define _VECTORS_SIZE 80
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 512
#define RAMEND 0x02FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x87
#endif /* #ifdef _AVR_ATA664251_H_INCLUDED */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */
/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */
#ifndef _AVR_IOAT94K_H_
#define _AVR_IOAT94K_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "ioat94k.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* UART1 Baud Rate Register */
#define UBRR1 _SFR_IO8(0x00)
/* UART1 Control and Status Registers */
#define UCSR1B _SFR_IO8(0x01)
#define UCSR1A _SFR_IO8(0x02)
/* UART1 I/O Data Register */
#define UDR1 _SFR_IO8(0x03)
/* 0x04 reserved */
/* Input Pins, Port E */
#define PINE _SFR_IO8(0x05)
/* Data Direction Register, Port E */
#define DDRE _SFR_IO8(0x06)
/* Data Register, Port E */
#define PORTE _SFR_IO8(0x07)
/* On Chip Debug Register (reserved) */
#define OCDR _SFR_IO8(0x08)
/* UART0 Baud Rate Register */
#define UBRR0 _SFR_IO8(0x09)
/* UART0 Control and Status Registers */
#define UCSR0B _SFR_IO8(0x0A)
#define UCSR0A _SFR_IO8(0x0B)
/* UART0 I/O Data Register */
#define UDR0 _SFR_IO8(0x0C)
/* 0x0D..0x0F reserved */
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* FPGA I/O Select Control Register */
#define FISCR _SFR_IO8(0x13)
/* FPGA I/O Select Registers A, B, C, D */
#define FISUA _SFR_IO8(0x14)
#define FISUB _SFR_IO8(0x15)
#define FISUC _SFR_IO8(0x16)
#define FISUD _SFR_IO8(0x17)
/* FPGA Cache Logic(R) registers (top secret, under NDA) */
#define FPGAX _SFR_IO8(0x18)
#define FPGAY _SFR_IO8(0x19)
#define FPGAZ _SFR_IO8(0x1A)
#define FPGAD _SFR_IO8(0x1B)
/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
/* 2-wire Serial Bit Rate Register */
#define TWBR _SFR_IO8(0x1C)
/* 2-wire Serial Status Register */
#define TWSR _SFR_IO8(0x1D)
/* 2-wire Serial (Slave) Address Register */
#define TWAR _SFR_IO8(0x1E)
/* 2-wire Serial Data Register */
#define TWDR _SFR_IO8(0x1F)
/* UART Baud Register High */
#define UBRRH _SFR_IO8(0x20)
#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Timer/Counter2 Output Compare Register */
#define OCR2 _SFR_IO8(0x22)
/* Timer/Counter2 (8-bit) */
#define TCNT2 _SFR_IO8(0x23)
/* Timer/Counter1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* Asynchronous mode StatuS Register */
#define ASSR _SFR_IO8(0x26)
/* Timer/Counter2 Control Register */
#define TCCR2 _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare RegisterB */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare RegisterA */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter1 Control Register B */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter1 Control Register A */
#define TCCR1A _SFR_IO8(0x2F)
/* Special Function IO Register */
#define SFIOR _SFR_IO8(0x30)
/* Timer/Counter0 Output Compare Register */
#define OCR0 _SFR_IO8(0x31)
/* Timer/Counter0 (8-bit) */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* 0x34 reserved */
/* MCU Control/Status Register */
#define MCUR _SFR_IO8(0x35)
/* 2-wire Serial Control Register */
#define TWCR _SFR_IO8(0x36)
/* 0x37 reserved */
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK Register */
#define TIMSK _SFR_IO8(0x39)
/* Software Control Register */
#define SFTCR _SFR_IO8(0x3A)
/* External Interrupt Mask/Flag Register */
#define EIMF _SFR_IO8(0x3B)
/* 0x3C reserved */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */
#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */
#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */
#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */
#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */
#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */
#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */
#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */
#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */
#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */
#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */
#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */
#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */
#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */
#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */
#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */
#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */
#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */
#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */
#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */
#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */
#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */
#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */
#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */
#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */
#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */
#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */
#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */
#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */
#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */
#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */
#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */
#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */
#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */
#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */
#define _VECTORS_SIZE 144
/* Bit numbers (SFRs alphabetically sorted) */
/* ASSR */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* DDRE */
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* EIMF */
#define INTF3 7
#define INTF2 6
#define INTF1 5
#define INTF0 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* FISCR */
#define FIADR 7
#define XFIS1 1
#define XFIS0 0
/* FISUA */
#define FIF3 7
#define FIF2 6
#define FIF1 5
#define FIF0 4
#define FINT3 3
#define FINT2 2
#define FINT1 1
#define FINT0 0
/* FISUB */
#define FIF7 7
#define FIF6 6
#define FIF5 5
#define FIF4 4
#define FINT7 3
#define FINT6 2
#define FINT5 1
#define FINT4 0
/* FISUC */
#define FIF11 7
#define FIF10 6
#define FIF9 5
#define FIF8 4
#define FINT11 3
#define FINT10 2
#define FINT9 1
#define FINT8 0
/* FISUD */
#define FIF15 7
#define FIF14 6
#define FIF13 5
#define FIF12 4
#define FINT15 3
#define FINT14 2
#define FINT13 1
#define FINT12 0
/* MCUR */
#define JTRF 7
#define JTD 6
#define SE 5
#define SM1 4
#define SM0 3
#define PORF 2
#define WDRF 1
#define EXTRF 0
/* OCDR (reserved) */
#define IDRD 7
/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* PINE */
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* PORTE */
/*
PE7 = IC1 / INT3 (alternate)
PE6 = OC1A / INT2 (alternate)
PE5 = OC1B / INT1 (alternate)
PE4 = ET11 / INT0 (alternate)
PE3 = OC2 / RX1 (alternate)
PE2 = / TX1 (alternate)
PE1 = OC0 / RX0 (alternate)
PE0 = ET0 / TX0 (alternate)
*/
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
/* SFIOR */
#define PSR2 1
#define PSR10 0
/* SFTCR */
#define FMXOR 3
#define WDTS 2
#define DBG 1
#define SRST 0
/* TCCR0 */
#define FOC0 7
#define PWM0 6
#define COM01 5
#define COM00 4
#define CTC0 3
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define PWM11 1
#define PWM10 0
/* TCCR1B */
#define ICNC1 7
#define ICES1 6
#define ICPE 5
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* TCCR2 */
#define FOC2 7
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* TIFR */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define TOV2 4
#define ICF1 3
#define OCF2 2
#define TOV0 1
#define OCF0 0
/* TIMSK */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define TOIE2 4
#define TICIE1 3
#define OCIE2 2
#define TOIE0 1
#define OCIE0 0
/* TWAR */
/* #define TWA 1 */ /* TWA is bits 7:1 */
#define TWGCE 0
/* TWCR */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
#define TWIE 0
/* TWSR */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
/* UBRRHI
Bits 11..8 of UART1 are bits 7..4 of UBRRHI.
Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */
/* #define UBRRHI1 4 */
/* #define UBRRHI0 0 */
/* UCSR0A */
#define RXC0 7
#define TXC0 6
#define UDRE0 5
#define FE0 4
#define OR0 3
#define U2X0 1
#define MPCM0 0
/* UCSR0B */
#define RXCIE0 7
#define TXCIE0 6
#define UDRIE0 5
#define RXEN0 4
#define TXEN0 3
#define CHR90 2
#define RXB80 1
#define TXB80 0
/* UCSR1A */
#define RXC1 7
#define TXC1 6
#define UDRE1 5
#define FE1 4
#define OR1 3
#define U2X1 1
#define MPCM1 0
/* UCSR1B */
#define RXCIE1 7
#define TXCIE1 6
#define UDRIE1 5
#define RXEN1 4
#define TXEN1 3
#define CHR91 2
#define RXB81 1
#define TXB81 0
/* WDTCR */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/*
Last memory addresses - depending on configuration, it is possible
to have 20K-32K of program memory and 4K-16K of data memory
(all in the same 36K total of SRAM, loaded from external EEPROM).
*/
#ifndef RAMSTART
#define RAMSTART 0x60
#endif
#ifndef RAMEND
#define RAMEND 0x0FFF
#endif
#ifndef XRAMEND
#define XRAMEND RAMEND
#endif
#define E2END 0
#ifndef FLASHEND
#define FLASHEND 0x7FFF
#endif
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
#endif /* _AVR_IOAT94K_H_ */

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/* Copyright (c) 2004,2005, Colin O'Flynn <coflynn@newae.com>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */
/* iocan128.h - definitions for CAN128 */
#ifndef _AVR_IOCAN128_H_
#define _AVR_IOCAN128_H_ 1
#include <avr/iocanxx.h>
/* Constants */
#define SPM_PAGESIZE 256
#define RAMSTART 0x100
#define RAMEND 0x10FF /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x0FFF
#define E2PAGESIZE 8
#define FLASHEND 0x1FFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x97
#define SIGNATURE_2 0x81
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* _AVR_IOCAN128_H_ */

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/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
/* iocan32.h - definitions for CAN32 */
#ifndef _AVR_IOCAN32_H_
#define _AVR_IOCAN32_H_ 1
#include <avr/iocanxx.h>
/* Constants */
#define SPM_PAGESIZE 256
#define RAMSTART 0x100
#define RAMEND 0x08FF /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x03FF
#define E2PAGESIZE 8
#define FLASHEND 0x7FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x81
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* _AVR_IOCAN32_H_ */

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/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
/* iocan64.h - definitions for CAN64 */
#ifndef _AVR_IOCAN64_H_
#define _AVR_IOCAN64_H_ 1
#include <avr/iocanxx.h>
/* Constants */
#define SPM_PAGESIZE 256
#define RAMSTART 0x100
#define RAMEND 0x10FF /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x07FF
#define E2PAGESIZE 8
#define FLASHEND 0xFFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x96
#define SIGNATURE_2 0x81
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* _AVR_IOCAN64_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */
/* avr/iom103.h - definitions for ATmega103 */
#ifndef _AVR_IOM103_H_
#define _AVR_IOM103_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom103.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* Input Pins, Port F */
#define PINF _SFR_IO8(0x00)
/* Input Pins, Port E */
#define PINE _SFR_IO8(0x01)
/* Data Direction Register, Port E */
#define DDRE _SFR_IO8(0x02)
/* Data Register, Port E */
#define PORTE _SFR_IO8(0x03)
/* ADC Data Register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
/* ADC Control and status register */
#define ADCSR _SFR_IO8(0x06)
/* ADC Multiplexer select */
#define ADMUX _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART Baud Rate Register */
#define UBRR _SFR_IO8(0x09)
/* UART Control Register */
#define UCR _SFR_IO8(0x0A)
/* UART Status Register */
#define USR _SFR_IO8(0x0B)
/* UART I/O Data Register */
#define UDR _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Timer2 Output Compare Register */
#define OCR2 _SFR_IO8(0x23)
/* Timer/Counter 2 */
#define TCNT2 _SFR_IO8(0x24)
/* Timer/Counter 2 Control register */
#define TCCR2 _SFR_IO8(0x25)
/* T/C 1 Input Capture Register */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter 1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter 1 Control and Status Register */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter 1 Control Register */
#define TCCR1A _SFR_IO8(0x2F)
/* Timer/Counter 0 Asynchronous Control & Status Register */
#define ASSR _SFR_IO8(0x30)
/* Output Compare Register 0 */
#define OCR0 _SFR_IO8(0x31)
/* Timer/Counter 0 */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter 0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x36)
/* Timer/Counter Interrupt MaSK register */
#define TIMSK _SFR_IO8(0x37)
/* <20>xternal Interrupt Flag Register */
#define EIFR _SFR_IO8(0x38)
/* External Interrupt MaSK register */
#define EIMSK _SFR_IO8(0x39)
/* External Interrupt Control Register */
#define EICR _SFR_IO8(0x3A)
/* RAM Page Z select register */
#define RAMPZ _SFR_IO8(0x3B)
/* XDIV Divide control register */
#define XDIV _SFR_IO8(0x3C)
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* External Interrupt 2 */
#define INT2_vect_num 3
#define INT2_vect _VECTOR(3)
#define SIG_INTERRUPT2 _VECTOR(3)
/* External Interrupt 3 */
#define INT3_vect_num 4
#define INT3_vect _VECTOR(4)
#define SIG_INTERRUPT3 _VECTOR(4)
/* External Interrupt 4 */
#define INT4_vect_num 5
#define INT4_vect _VECTOR(5)
#define SIG_INTERRUPT4 _VECTOR(5)
/* External Interrupt 5 */
#define INT5_vect_num 6
#define INT5_vect _VECTOR(6)
#define SIG_INTERRUPT5 _VECTOR(6)
/* External Interrupt 6 */
#define INT6_vect_num 7
#define INT6_vect _VECTOR(7)
#define SIG_INTERRUPT6 _VECTOR(7)
/* External Interrupt 7 */
#define INT7_vect_num 8
#define INT7_vect _VECTOR(8)
#define SIG_INTERRUPT7 _VECTOR(8)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 9
#define TIMER2_COMP_vect _VECTOR(9)
#define SIG_OUTPUT_COMPARE2 _VECTOR(9)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 10
#define TIMER2_OVF_vect _VECTOR(10)
#define SIG_OVERFLOW2 _VECTOR(10)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 11
#define TIMER1_CAPT_vect _VECTOR(11)
#define SIG_INPUT_CAPTURE1 _VECTOR(11)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 12
#define TIMER1_COMPA_vect _VECTOR(12)
#define SIG_OUTPUT_COMPARE1A _VECTOR(12)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 13
#define TIMER1_COMPB_vect _VECTOR(13)
#define SIG_OUTPUT_COMPARE1B _VECTOR(13)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 14
#define TIMER1_OVF_vect _VECTOR(14)
#define SIG_OVERFLOW1 _VECTOR(14)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 15
#define TIMER0_COMP_vect _VECTOR(15)
#define SIG_OUTPUT_COMPARE0 _VECTOR(15)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 16
#define TIMER0_OVF_vect _VECTOR(16)
#define SIG_OVERFLOW0 _VECTOR(16)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 17
#define SPI_STC_vect _VECTOR(17)
#define SIG_SPI _VECTOR(17)
/* UART, Rx Complete */
#define UART_RX_vect_num 18
#define UART_RX_vect _VECTOR(18)
#define SIG_UART_RECV _VECTOR(18)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 19
#define UART_UDRE_vect _VECTOR(19)
#define SIG_UART_DATA _VECTOR(19)
/* UART, Tx Complete */
#define UART_TX_vect_num 20
#define UART_TX_vect _VECTOR(20)
#define SIG_UART_TRANS _VECTOR(20)
/* ADC Conversion Complete */
#define ADC_vect_num 21
#define ADC_vect _VECTOR(21)
#define SIG_ADC _VECTOR(21)
/* EEPROM Ready */
#define EE_READY_vect_num 22
#define EE_READY_vect _VECTOR(22)
#define SIG_EEPROM_READY _VECTOR(22)
/* Analog Comparator */
#define ANALOG_COMP_vect_num 23
#define ANALOG_COMP_vect _VECTOR(23)
#define SIG_COMPARATOR _VECTOR(23)
#define _VECTORS_SIZE 96
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* XDIV Divide control register*/
#define XDIVEN 7
#define XDIV6 6
#define XDIV5 5
#define XDIV4 4
#define XDIV3 3
#define XDIV2 2
#define XDIV1 1
#define XDIV0 0
/* RAM Page Z select register */
#define RAMPZ0 0
/* External Interrupt Control Register */
#define ISC71 7
#define ISC70 6
#define ISC61 5
#define ISC60 4
#define ISC51 3
#define ISC50 2
#define ISC41 1
#define ISC40 0
/* External Interrupt MaSK register */
#define INT7 7
#define INT6 6
#define INT5 5
#define INT4 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* <20>xternal Interrupt Flag Register */
#define INTF7 7
#define INTF6 6
#define INTF5 5
#define INTF4 4
/* Timer/Counter Interrupt MaSK register */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
#define OCIE0 1
#define TOIE0 0
/* Timer/Counter Interrupt Flag Register */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
#define OCF0 1
#define TOV0 0
/* MCU general Control Register */
#define SRE 7
#define SRW 6
#define SE 5
#define SM1 4
#define SM0 3
/* MCU Status Register */
#define EXTRF 1
#define PORF 0
/* Timer/Counter 0 Control Register */
#define PWM0 6
#define COM01 5
#define COM00 4
#define CTC0 3
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 0 Asynchronous Control & Status Register */
#define AS0 3
#define TCN0UB 2
#define OCR0UB 1
#define TCR0UB 0
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define PWM11 1
#define PWM10 0
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter 2 Control register */
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* Data Register, Port E */
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
/* Data Direction Register, Port E */
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* Input Pins, Port E */
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* Input Pins, Port F */
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADC Control and status register */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADC Multiplexer select */
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define RAMSTART 0x60
#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/
#define XRAMEND 0xFFFF
#define E2END 0x0FFF
#define E2PAGESIZE 0
#define FLASHEND 0x1FFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */
#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */
#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x97
#define SIGNATURE_2 0x01
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_ADC _BV(SM0)
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_INTERRUPT1
#pragma GCC poison SIG_INTERRUPT2
#pragma GCC poison SIG_INTERRUPT3
#pragma GCC poison SIG_INTERRUPT4
#pragma GCC poison SIG_INTERRUPT5
#pragma GCC poison SIG_INTERRUPT6
#pragma GCC poison SIG_INTERRUPT7
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OUTPUT_COMPARE0
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison SIG_UART_RECV
#pragma GCC poison SIG_UART_DATA
#pragma GCC poison SIG_UART_TRANS
#pragma GCC poison SIG_ADC
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_COMPARATOR
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#endif /* _AVR_IOM103_H_ */

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/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
/* avr/iom1280.h - definitions for ATmega1280 */
#ifndef _AVR_IOM1280_H_
#define _AVR_IOM1280_H_ 1
#include <avr/iomxx0_1.h>
/* Constants */
#define SPM_PAGESIZE 256
#define RAMSTART 0x200
#define RAMEND 0x21FF
#define XRAMEND 0xFFFF
#define E2END 0xFFF
#define E2PAGESIZE 8
#define FLASHEND 0x1FFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x97
#define SIGNATURE_2 0x03
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
#endif /* _AVR_IOM1280_H_ */

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/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */
/* avr/iom1281.h - definitions for ATmega1281 */
#ifndef _AVR_IOM1281_H_
#define _AVR_IOM1281_H_ 1
#include <avr/iomxx0_1.h>
/* Constants */
#define SPM_PAGESIZE 256
#define RAMSTART (0x200)
#define RAMEND 0x21FF
#define XRAMEND 0xFFFF
#define E2END 0xFFF
#define E2PAGESIZE 8
#define FLASHEND 0x1FFFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x97
#define SIGNATURE_2 0x04
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
#endif /* _AVR_IOM1281_H_ */

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/* Copyright (c) 2004 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */
/* avr/iom16.h - definitions for ATmega16 */
#ifndef _AVR_IOM16_H_
#define _AVR_IOM16_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom16.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define TWBR _SFR_IO8(0x00)
#define TWSR _SFR_IO8(0x01)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_IO8(0x02)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_IO8(0x03)
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
#define ADCSRA _SFR_IO8(0x06)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADMUX _SFR_IO8(0x07)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
#define ACSR _SFR_IO8(0x08)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define UBRRL _SFR_IO8(0x09)
#define UCSRB _SFR_IO8(0x0A)
#define TXB8 0
#define RXB8 1
#define UCSZ2 2
#define TXEN 3
#define RXEN 4
#define UDRIE 5
#define TXCIE 6
#define RXCIE 7
#define UCSRA _SFR_IO8(0x0B)
#define MPCM 0
#define U2X 1
#define PE 2
#define DOR 3
#define FE 4
#define UDRE 5
#define TXC 6
#define RXC 7
#define UDR _SFR_IO8(0x0C)
#define SPCR _SFR_IO8(0x0D)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x0E)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x0F)
#define PIND _SFR_IO8(0x10)
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7
#define DDRD _SFR_IO8(0x11)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x12)
#define PD0 0
#define PD1 1
#define PD2 2
#define PD3 3
#define PD4 4
#define PD5 5
#define PD6 6
#define PD7 7
#define PINC _SFR_IO8(0x13)
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define PINC7 7
#define DDRC _SFR_IO8(0x14)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define DDC7 7
#define PORTC _SFR_IO8(0x15)
#define PC0 0
#define PC1 1
#define PC2 2
#define PC3 3
#define PC4 4
#define PC5 5
#define PC6 6
#define PC7 7
#define PINB _SFR_IO8(0x16)
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
#define DDRB _SFR_IO8(0x17)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x18)
#define PB0 0
#define PB1 1
#define PB2 2
#define PB3 3
#define PB4 4
#define PB5 5
#define PB6 6
#define PB7 7
#define PINA _SFR_IO8(0x19)
#define PINA0 0
#define PINA1 1
#define PINA2 2
#define PINA3 3
#define PINA4 4
#define PINA5 5
#define PINA6 6
#define PINA7 7
#define DDRA _SFR_IO8(0x1A)
#define DDA0 0
#define DDA1 1
#define DDA2 2
#define DDA3 3
#define DDA4 4
#define DDA5 5
#define DDA6 6
#define DDA7 7
#define PORTA _SFR_IO8(0x1B)
#define PA0 0
#define PA1 1
#define PA2 2
#define PA3 3
#define PA4 4
#define PA5 5
#define PA6 6
#define PA7 7
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
#define UCSRC _SFR_IO8(0x20)
#define UCPOL 0
#define UCSZ0 1
#define UCSZ1 2
#define USBS 3
#define UPM0 4
#define UPM1 5
#define UMSEL 6
#define URSEL 7
#define UBRRH _SFR_IO8(0x20)
#define URSEL 7
#define WDTCR _SFR_IO8(0x21)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDTOE 4
#define ASSR _SFR_IO8(0x22)
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3
#define OCR2 _SFR_IO8(0x23)
#define TCNT2 _SFR_IO8(0x24)
#define TCCR2 _SFR_IO8(0x25)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM21 3
#define COM20 4
#define COM21 5
#define WGM20 6
#define FOC2 7
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
#define TCCR1B _SFR_IO8(0x2E)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1A _SFR_IO8(0x2F)
#define WGM10 0
#define WGM11 1
#define FOC1B 2
#define FOC1A 3
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
/*
The ADHSM bit has been removed from all documentation,
as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
#define SFIOR _SFR_IO8(0x30)
#define PSR10 0
#define PSR2 1
#define PUD 2
#define ACME 3
#define ADTS0 5
#define ADTS1 6
#define ADTS2 7
#define OSCCAL _SFR_IO8(0x31)
#define OCDR _SFR_IO8(0x31)
#define TCNT0 _SFR_IO8(0x32)
#define TCCR0 _SFR_IO8(0x33)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM00 4
#define COM01 5
#define WGM00 6
#define FOC0 7
#define MCUCSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define JTRF 4
#define ISC2 6
#define JTD 7
#define MCUCR _SFR_IO8(0x35)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define SM0 4
#define SM1 5
#define SE 6
#define SM2 7
#define TWCR _SFR_IO8(0x36)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define SPMCR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
#define TIFR _SFR_IO8(0x38)
#define TOV0 0
#define OCF0 1
#define TOV1 2
#define OCF1B 3
#define OCF1A 4
#define ICF1 5
#define TOV2 6
#define OCF2 7
#define TIMSK _SFR_IO8(0x39)
#define TOIE0 0
#define OCIE0 1
#define TOIE1 2
#define OCIE1B 3
#define OCIE1A 4
#define TICIE1 5
#define TOIE2 6
#define OCIE2 7
#define GIFR _SFR_IO8(0x3A)
#define INTF2 5
#define INTF0 6
#define INTF1 7
#define GICR _SFR_IO8(0x3B)
#define IVCE 0
#define IVSEL 1
#define INT2 5
#define INT0 6
#define INT1 7
#define OCR0 _SFR_IO8(0x3C)
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
/* Interrupt vectors */
/* Vector 0 is the reset vector. */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 3
#define TIMER2_COMP_vect _VECTOR(3)
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 4
#define TIMER2_OVF_vect _VECTOR(4)
#define SIG_OVERFLOW2 _VECTOR(4)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 5
#define TIMER1_CAPT_vect _VECTOR(5)
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 6
#define TIMER1_COMPA_vect _VECTOR(6)
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 7
#define TIMER1_COMPB_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 8
#define TIMER1_OVF_vect _VECTOR(8)
#define SIG_OVERFLOW1 _VECTOR(8)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 9
#define TIMER0_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW0 _VECTOR(9)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 10
#define SPI_STC_vect _VECTOR(10)
#define SIG_SPI _VECTOR(10)
/* USART, Rx Complete */
#define USART_RXC_vect_num 11
#define USART_RXC_vect _VECTOR(11)
#define SIG_USART_RECV _VECTOR(11)
#define SIG_UART_RECV _VECTOR(11)
/* USART Data Register Empty */
#define USART_UDRE_vect_num 12
#define USART_UDRE_vect _VECTOR(12)
#define SIG_USART_DATA _VECTOR(12)
#define SIG_UART_DATA _VECTOR(12)
/* USART, Tx Complete */
#define USART_TXC_vect_num 13
#define USART_TXC_vect _VECTOR(13)
#define SIG_USART_TRANS _VECTOR(13)
#define SIG_UART_TRANS _VECTOR(13)
/* ADC Conversion Complete */
#define ADC_vect_num 14
#define ADC_vect _VECTOR(14)
#define SIG_ADC _VECTOR(14)
/* EEPROM Ready */
#define EE_RDY_vect_num 15
#define EE_RDY_vect _VECTOR(15)
#define SIG_EEPROM_READY _VECTOR(15)
/* Analog Comparator */
#define ANA_COMP_vect_num 16
#define ANA_COMP_vect _VECTOR(16)
#define SIG_COMPARATOR _VECTOR(16)
/* 2-wire Serial Interface */
#define TWI_vect_num 17
#define TWI_vect _VECTOR(17)
#define SIG_2WIRE_SERIAL _VECTOR(17)
/* External Interrupt Request 2 */
#define INT2_vect_num 18
#define INT2_vect _VECTOR(18)
#define SIG_INTERRUPT2 _VECTOR(18)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 19
#define TIMER0_COMP_vect _VECTOR(19)
#define SIG_OUTPUT_COMPARE0 _VECTOR(19)
/* Store Program Memory Ready */
#define SPM_RDY_vect_num 20
#define SPM_RDY_vect _VECTOR(20)
#define SIG_SPM_READY _VECTOR(20)
#define _VECTORS_SIZE 84
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART (0x60)
#define RAMEND 0x45F
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_BODEN (unsigned char)~_BV(6)
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_CKOPT (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x03
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_INTERRUPT1
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison SIG_USART_RECV
#pragma GCC poison SIG_UART_RECV
#pragma GCC poison SIG_USART_DATA
#pragma GCC poison SIG_UART_DATA
#pragma GCC poison SIG_USART_TRANS
#pragma GCC poison SIG_UART_TRANS
#pragma GCC poison SIG_ADC
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_COMPARATOR
#pragma GCC poison SIG_2WIRE_SERIAL
#pragma GCC poison SIG_INTERRUPT2
#pragma GCC poison SIG_OUTPUT_COMPARE0
#pragma GCC poison SIG_SPM_READY
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#define SLEEP_MODE_IDLE (0x00<<4)
#define SLEEP_MODE_ADC (0x01<<4)
#define SLEEP_MODE_PWR_DOWN (0x02<<4)
#define SLEEP_MODE_PWR_SAVE (0x03<<4)
#define SLEEP_MODE_STANDBY (0x0A<<4)
#define SLEEP_MODE_EXT_STANDBY (0x0B<<4)
#endif /* _AVR_IOM16_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom161.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */
/* avr/iom161.h - definitions for ATmega161 */
#ifndef _AVR_IOM161_H_
#define _AVR_IOM161_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom161.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/* UART1 Baud Rate Register */
#define UBRR1 _SFR_IO8(0x00)
/* UART1 Control and Status Registers */
#define UCSR1B _SFR_IO8(0x01)
#define UCSR1A _SFR_IO8(0x02)
/* UART1 I/O Data Register */
#define UDR1 _SFR_IO8(0x03)
/* 0x04 reserved */
/* Input Pins, Port E */
#define PINE _SFR_IO8(0x05)
/* Data Direction Register, Port E */
#define DDRE _SFR_IO8(0x06)
/* Data Register, Port E */
#define PORTE _SFR_IO8(0x07)
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
/* UART0 Baud Rate Register */
#define UBRR0 _SFR_IO8(0x09)
/* UART0 Control and Status Registers */
#define UCSR0B _SFR_IO8(0x0A)
#define UCSR0A _SFR_IO8(0x0B)
/* UART0 I/O Data Register */
#define UDR0 _SFR_IO8(0x0C)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
/* SPI Status Register */
#define SPSR _SFR_IO8(0x0E)
/* SPI I/O Data Register */
#define SPDR _SFR_IO8(0x0F)
/* Input Pins, Port D */
#define PIND _SFR_IO8(0x10)
/* Data Direction Register, Port D */
#define DDRD _SFR_IO8(0x11)
/* Data Register, Port D */
#define PORTD _SFR_IO8(0x12)
/* Input Pins, Port C */
#define PINC _SFR_IO8(0x13)
/* Data Direction Register, Port C */
#define DDRC _SFR_IO8(0x14)
/* Data Register, Port C */
#define PORTC _SFR_IO8(0x15)
/* Input Pins, Port B */
#define PINB _SFR_IO8(0x16)
/* Data Direction Register, Port B */
#define DDRB _SFR_IO8(0x17)
/* Data Register, Port B */
#define PORTB _SFR_IO8(0x18)
/* Input Pins, Port A */
#define PINA _SFR_IO8(0x19)
/* Data Direction Register, Port A */
#define DDRA _SFR_IO8(0x1A)
/* Data Register, Port A */
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* UART Baud Register HIgh */
#define UBRRH _SFR_IO8(0x20)
/* Watchdog Timer Control Register */
#define WDTCR _SFR_IO8(0x21)
/* Timer/Counter2 Output Compare Register */
#define OCR2 _SFR_IO8(0x22)
/* Timer/Counter2 (8-bit) */
#define TCNT2 _SFR_IO8(0x23)
/* Timer/Counter1 Input Capture Register */
#define ICR1 _SFR_IO16(0x24)
#define ICR1L _SFR_IO8(0x24)
#define ICR1H _SFR_IO8(0x25)
/* ASynchronous mode Status Register */
#define ASSR _SFR_IO8(0x26)
/* Timer/Counter2 Control Register */
#define TCCR2 _SFR_IO8(0x27)
/* Timer/Counter1 Output Compare RegisterB */
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
/* Timer/Counter1 Output Compare RegisterA */
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
/* Timer/Counter1 */
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
/* Timer/Counter1 Control Register B */
#define TCCR1B _SFR_IO8(0x2E)
/* Timer/Counter1 Control Register A */
#define TCCR1A _SFR_IO8(0x2F)
/* Special Function IO Register */
#define SFIOR _SFR_IO8(0x30)
/* Timer/Counter0 Output Compare Register */
#define OCR0 _SFR_IO8(0x31)
/* Timer/Counter0 (8-bit) */
#define TCNT0 _SFR_IO8(0x32)
/* Timer/Counter0 Control Register */
#define TCCR0 _SFR_IO8(0x33)
/* MCU general Status Register */
#define MCUSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
/* Extended MCU general Control Register */
#define EMCUCR _SFR_IO8(0x36)
/* Store Program Memory Control Register */
#define SPMCR _SFR_IO8(0x37)
/* Timer/Counter Interrupt Flag Register */
#define TIFR _SFR_IO8(0x38)
/* Timer/Counter Interrupt MaSK Register */
#define TIMSK _SFR_IO8(0x39)
/* General Interrupt Flag Register */
#define GIFR _SFR_IO8(0x3A)
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C reserved */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* External Interrupt 2 */
#define INT2_vect_num 3
#define INT2_vect _VECTOR(3)
#define SIG_INTERRUPT2 _VECTOR(3)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 4
#define TIMER2_COMP_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 5
#define TIMER2_OVF_vect _VECTOR(5)
#define SIG_OVERFLOW2 _VECTOR(5)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 6
#define TIMER1_CAPT_vect _VECTOR(6)
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 7
#define TIMER1_COMPA_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 8
#define TIMER1_COMPB_vect _VECTOR(8)
#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 9
#define TIMER1_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW1 _VECTOR(9)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 10
#define TIMER0_COMP_vect _VECTOR(10)
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 11
#define TIMER0_OVF_vect _VECTOR(11)
#define SIG_OVERFLOW0 _VECTOR(11)
/* Serial Transfer Complete */
#define SPI_STC_vect_num 12
#define SPI_STC_vect _VECTOR(12)
#define SIG_SPI _VECTOR(12)
/* UART0, Rx Complete */
#define UART0_RX_vect_num 13
#define UART0_RX_vect _VECTOR(13)
#define SIG_UART0_RECV _VECTOR(13)
/* UART1, Rx Complete */
#define UART1_RX_vect_num 14
#define UART1_RX_vect _VECTOR(14)
#define SIG_UART1_RECV _VECTOR(14)
/* UART0 Data Register Empty */
#define UART0_UDRE_vect_num 15
#define UART0_UDRE_vect _VECTOR(15)
#define SIG_UART0_DATA _VECTOR(15)
/* UART1 Data Register Empty */
#define UART1_UDRE_vect_num 16
#define UART1_UDRE_vect _VECTOR(16)
#define SIG_UART1_DATA _VECTOR(16)
/* UART0, Tx Complete */
#define UART0_TX_vect_num 17
#define UART0_TX_vect _VECTOR(17)
#define SIG_UART0_TRANS _VECTOR(17)
/* UART1, Tx Complete */
#define UART1_TX_vect_num 18
#define UART1_TX_vect _VECTOR(18)
#define SIG_UART1_TRANS _VECTOR(18)
/* EEPROM Ready */
#define EE_RDY_vect_num 19
#define EE_RDY_vect _VECTOR(19)
#define SIG_EEPROM_READY _VECTOR(19)
/* Analog Comparator */
#define ANA_COMP_vect_num 20
#define ANA_COMP_vect _VECTOR(20)
#define SIG_COMPARATOR _VECTOR(20)
#define _VECTORS_SIZE 84
/* Bit numbers */
/* GIMSK */
#define INT1 7
#define INT0 6
#define INT2 5
/* GIFR */
#define INTF1 7
#define INTF0 6
#define INTF2 5
/* TIMSK */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define TOIE2 4
#define TICIE1 3
#define OCIE2 2
#define TOIE0 1
#define OCIE0 0
/* TIFR */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define TOV2 4
#define ICF1 3
#define OCF2 2
#define TOV0 1
#define OCF0 0
/* MCUCR */
#define SRE 7
#define SRW10 6
#define SE 5
#define SM1 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* EMCUCR */
#define SM0 7
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW01 3
#define SRW00 2
#define SRW11 1
#define ISC2 0
/* SPMCR */
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* SFIOR */
#define PSR2 1
#define PSR10 0
/* TCCR0 */
#define FOC0 7
#define PWM0 6
#define COM01 5
#define COM00 4
#define CTC0 3
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR2 */
#define FOC2 7
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* ASSR */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define PWM11 1
#define PWM10 0
/* TCCR1B */
#define ICNC1 7
#define ICES1 6
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* WDTCR */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* PINA */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/*
PB7 = SCK
PB6 = MISO
PB5 = MOSI
PB4 = SS#
PB3 = TXD1 / AIN1
PB2 = RXD1 / AIN0
PB1 = OC2 / T1
PB0 = OC0 / T0
*/
/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* PORTC */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* DDRC */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* PINC */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/*
PD7 = RD#
PD6 = WR#
PD5 = TOSC2 / OC1A
PD4 = TOSC1
PD3 = INT1
PD2 = INT0
PD1 = TXD0
PD0 = RXD0
*/
/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/*
PE2 = ALE
PE1 = OC1B
PE0 = ICP / INT2
*/
/* PORTE */
#define PE2 2
#define PE1 1
#define PE0 0
/* DDRE */
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* PINE */
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* SPSR */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UCSR0A, UCSR1A */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
#define U2X 1
#define MPCM 0
/* UCSR0B, UCSR1B */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* ACSR */
#define ACD 7
#define AINBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART 0x60
#define RAMEND 0x45F
#define XRAMEND 0xFFFF
#define E2END 0x1FF
#define E2PAGESIZE 0
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 1
/* Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_BOOTRST (unsigned char)~_BV(6)
#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x01
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN 1
#define SLEEP_MODE_PWR_SAVE 2
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_INTERRUPT1
#pragma GCC poison SIG_INTERRUPT2
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OUTPUT_COMPARE0
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison SIG_UART0_RECV
#pragma GCC poison SIG_UART1_RECV
#pragma GCC poison SIG_UART0_DATA
#pragma GCC poison SIG_UART1_DATA
#pragma GCC poison SIG_UART0_TRANS
#pragma GCC poison SIG_UART1_TRANS
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_COMPARATOR
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#endif /* _AVR_IOM161_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom162.h
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686
arduino/hardware/tools/avr/avr/include/avr/iom163.h
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */
/* avr/iom163.h - definitions for ATmega163 */
#ifndef _AVR_IOM163_H_
#define _AVR_IOM163_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom163.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
#define TWBR _SFR_IO8(0x00)
#define TWSR _SFR_IO8(0x01)
#define TWAR _SFR_IO8(0x02)
#define TWDR _SFR_IO8(0x03)
/* ADC */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCW _SFR_IO16(0x04)
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
#define ADCSR _SFR_IO8(0x06)
#define ADMUX _SFR_IO8(0x07)
/* analog comparator */
#define ACSR _SFR_IO8(0x08)
/* UART */
#define UBRR _SFR_IO8(0x09)
#define UCSRB _SFR_IO8(0x0A)
#define UCSRA _SFR_IO8(0x0B)
#define UDR _SFR_IO8(0x0C)
/* SPI */
#define SPCR _SFR_IO8(0x0D)
#define SPSR _SFR_IO8(0x0E)
#define SPDR _SFR_IO8(0x0F)
/* Port D */
#define PIND _SFR_IO8(0x10)
#define DDRD _SFR_IO8(0x11)
#define PORTD _SFR_IO8(0x12)
/* Port C */
#define PINC _SFR_IO8(0x13)
#define DDRC _SFR_IO8(0x14)
#define PORTC _SFR_IO8(0x15)
/* Port B */
#define PINB _SFR_IO8(0x16)
#define DDRB _SFR_IO8(0x17)
#define PORTB _SFR_IO8(0x18)
/* Port A */
#define PINA _SFR_IO8(0x19)
#define DDRA _SFR_IO8(0x1A)
#define PORTA _SFR_IO8(0x1B)
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
#define UBRRHI _SFR_IO8(0x20)
#define WDTCR _SFR_IO8(0x21)
#define ASSR _SFR_IO8(0x22)
/* Timer 2 */
#define OCR2 _SFR_IO8(0x23)
#define TCNT2 _SFR_IO8(0x24)
#define TCCR2 _SFR_IO8(0x25)
/* Timer 1 */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
#define TCCR1B _SFR_IO8(0x2E)
#define TCCR1A _SFR_IO8(0x2F)
#define SFIOR _SFR_IO8(0x30)
#define OSCCAL _SFR_IO8(0x31)
/* Timer 0 */
#define TCNT0 _SFR_IO8(0x32)
#define TCCR0 _SFR_IO8(0x33)
#define MCUSR _SFR_IO8(0x34)
#define MCUCR _SFR_IO8(0x35)
#define TWCR _SFR_IO8(0x36)
#define SPMCR _SFR_IO8(0x37)
#define TIFR _SFR_IO8(0x38)
#define TIMSK _SFR_IO8(0x39)
#define GIFR _SFR_IO8(0x3A)
#define GIMSK _SFR_IO8(0x3B)
/* 0x3C reserved */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
/* External Interrupt 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 3
#define TIMER2_COMP_vect _VECTOR(3)
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 4
#define TIMER2_OVF_vect _VECTOR(4)
#define SIG_OVERFLOW2 _VECTOR(4)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 5
#define TIMER1_CAPT_vect _VECTOR(5)
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 6
#define TIMER1_COMPA_vect _VECTOR(6)
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect_num 7
#define TIMER1_COMPB_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 8
#define TIMER1_OVF_vect _VECTOR(8)
#define SIG_OVERFLOW1 _VECTOR(8)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 9
#define TIMER0_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW0 _VECTOR(9)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 10
#define SPI_STC_vect _VECTOR(10)
#define SIG_SPI _VECTOR(10)
/* UART, RX Complete */
#define UART_RX_vect_num 11
#define UART_RX_vect _VECTOR(11)
#define SIG_UART_RECV _VECTOR(11)
/* UART Data Register Empty */
#define UART_UDRE_vect_num 12
#define UART_UDRE_vect _VECTOR(12)
#define SIG_UART_DATA _VECTOR(12)
/* UART, TX Complete */
#define UART_TX_vect_num 13
#define UART_TX_vect _VECTOR(13)
#define SIG_UART_TRANS _VECTOR(13)
/* ADC Conversion Complete */
#define ADC_vect_num 14
#define ADC_vect _VECTOR(14)
#define SIG_ADC _VECTOR(14)
/* EEPROM Ready */
#define EE_RDY_vect_num 15
#define EE_RDY_vect _VECTOR(15)
#define SIG_EEPROM_READY _VECTOR(15)
/* Analog Comparator */
#define ANA_COMP_vect_num 16
#define ANA_COMP_vect _VECTOR(16)
#define SIG_COMPARATOR _VECTOR(16)
/* 2-Wire Serial Interface */
#define TWI_vect_num 17
#define TWI_vect _VECTOR(17)
#define SIG_2WIRE_SERIAL _VECTOR(17)
#define _VECTORS_SIZE 72
/* Bit numbers */
/* GIMSK */
#define INT1 7
#define INT0 6
/* bit 5 reserved, undefined */
/* bits 4-0 reserved */
/* GIFR */
#define INTF1 7
#define INTF0 6
/* bits 5-0 reserved */
/* TIMSK */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
/* bit 1 reserved */
#define TOIE0 0
/* TIFR */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
/* bit 1 reserved, undefined */
#define TOV0 0
/* SPMCR */
/* bit 7 reserved */
#define ASB 6
/* bit 5 reserved */
#define ASRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* TWCR */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
/* bit 1 reserved */
#define TWIE 0
/* TWAR */
#define TWGCE 0
/* TWSR */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
/* bits 2-0 reserved */
/* MCUCR */
/* bit 7 reserved */
#define SE 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* MCUSR */
/* bits 7-4 reserved */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* SFIOR */
/* bits 7-4 reserved */
#define ACME 3
#define PUD 2
#define PSR2 1
#define PSR10 0
/* TCCR0 */
/* bits 7-3 reserved */
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR2 */
#define FOC2 7
#define PWM2 6
#define COM21 5
#define COM20 4
#define CTC2 3
#define CS22 2
#define CS21 1
#define CS20 0
/* ASSR */
/* bits 7-4 reserved */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define PWM11 1
#define PWM10 0
/* TCCR1B */
#define ICNC1 7
#define ICES1 6
/* bits 5-4 reserved */
#define CTC1 3
#define CS12 2
#define CS11 1
#define CS10 0
/* WDTCR */
/* bits 7-5 reserved */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* PA7-PA0 = ADC7-ADC0 */
/* PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* PINA */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/*
PB7 = SCK
PB6 = MISO
PB5 = MOSI
PB4 = SS#
PB3 = AIN1
PB2 = AIN0
PB1 = T1
PB0 = T0
*/
/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/*
PC7 = TOSC2
PC6 = TOSC1
PC1 = SDA
PC0 = SCL
*/
/* PORTC */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* DDRC */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* PINC */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/*
PD7 = OC2
PD6 = ICP
PD5 = OC1A
PD4 = OC1B
PD3 = INT1
PD2 = INT0
PD1 = TXD
PD0 = RXD
*/
/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPSR */
#define SPIF 7
#define WCOL 6
/* bits 5-1 reserved */
#define SPI2X 0
/* SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UCSRA */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
/* bit 2 reserved */
#define U2X 1
#define MPCM 0
/* UCSRB */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define CHR9 2
#define RXB8 1
#define TXB8 0
/* ACSR */
#define ACD 7
#define AINBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADCSR */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
#define MUX4 4
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART 0x60
#define RAMEND 0x45F
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 0
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_BODEN (unsigned char)~_BV(6)
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define HFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x02
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_ADC _BV(SM0)
#define SLEEP_MODE_PWR_DOWN _BV(SM1)
#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_INTERRUPT1
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison SIG_UART_RECV
#pragma GCC poison SIG_UART_DATA
#pragma GCC poison SIG_UART_TRANS
#pragma GCC poison SIG_ADC
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_COMPARATOR
#pragma GCC poison SIG_2WIRE_SERIAL
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#endif /* _AVR_IOM163_H_ */

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/* Copyright (c) 2005, 2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* avr/iom164.h - definitions for ATmega164 */
/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */
#ifndef _AVR_IOM164_H_
#define _AVR_IOM164_H_ 1
#include <avr/iomxx4.h>
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART (0x100)
#define RAMEND 0x04FF
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature (ATmega164P) */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x0A
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
#endif /* _AVR_IOM164_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom164a.h
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/*****************************************************************************
*
* Copyright (C) 2011 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#include "iom164.h"

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arduino/hardware/tools/avr/avr/include/avr/iom164p.h
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/*****************************************************************************
*
* Copyright (C) 2011 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#include "iom164.h"

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arduino/hardware/tools/avr/avr/include/avr/iom165.h
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/* Copyright (c) 2004,2005,2006 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom165.h 2231 2011-03-07 05:06:55Z arcanum $ */
/* avr/iom165.h - definitions for ATmega165 */
#ifndef _AVR_IOM165_H_
#define _AVR_IOM165_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom165.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
#define PORTA _SFR_IO8(0x02)
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
#define PORTE _SFR_IO8(0x0E)
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
#define PINF _SFR_IO8(0x0F)
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
#define DDRF _SFR_IO8(0x10)
#define DDF7 7
#define DDF6 6
#define DDF5 5
#define DDF4 4
#define DDF3 3
#define DDF2 2
#define DDF1 1
#define DDF0 0
#define PORTF _SFR_IO8(0x11)
#define PF7 7
#define PF6 6
#define PF5 5
#define PF4 4
#define PF3 3
#define PF2 2
#define PF1 1
#define PF0 0
#define PING _SFR_IO8(0x12)
#define PING4 4
#define PING3 3
#define PING2 2
#define PING1 1
#define PING0 0
#define DDRG _SFR_IO8(0x13)
#define DDG4 4
#define DDG3 3
#define DDG2 2
#define DDG1 1
#define DDG0 0
#define PORTG _SFR_IO8(0x14)
#define PG4 4
#define PG3 3
#define PG2 2
#define PG1 1
#define PG0 0
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
/* Reserved [0x18..0x1B] */
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define PCIF0 6
#define PCIF1 7
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define PCIE0 6
#define PCIE1 7
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEDR _SFR_IO8(0X20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
#define __EEPROM_REG_LOCATIONS__ 1F2021
#define GTCCR _SFR_IO8(0x23)
#define PSR10 0
#define PSR2 1
#define TSM 7
#define TCCR0A _SFR_IO8(0x24)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM0A0 4
#define COM0A1 5
#define WGM00 6
#define FOC0A 7
/* Reserved [0x25] */
#define TCNT0 _SFR_IO8(0X26)
#define OCR0A _SFR_IO8(0X27)
/* Reserved [0x28..0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0X2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define OCDR _SFR_IO8(0x31)
#define OCDR0 0
#define OCDR1 1
#define OCDR2 2
#define OCDR3 3
#define OCDR4 4
#define OCDR5 5
#define OCDR6 6
#define OCD 7 // The datasheet defines this but IMO it should be OCDR7.
#define OCDR7 7
#define IDRD 7
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define JTRF 4
#define MCUCR _SFR_IO8(0X35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define JTD 7
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
/* Reserved [0x6A] */
/* Combine PCMSK0 and PCMSK1 */
#define PCMSK _SFR_MEM16(0x6B)
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0X80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0X81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM21 3
#define COM2A0 4
#define COM2A1 5
#define WGM20 6
#define FOC2A 7
/* Reserved [0xB1] */
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
/* Reserved [0xB4..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3
#define EXCLK 4
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
/* Reserved [0xBB..0xBF] */
#define UCSRA _SFR_MEM8(0xC0)
#define MPCM 0
#define U2X 1
#define UPE 2
#define DOR 3
#define FE 4
#define UDRE 5
#define TXC 6
#define RXC 7
#define UCSRB _SFR_MEM8(0XC1)
#define TXB8 0
#define RXB8 1
#define UCSZ2 2
#define TXEN 3
#define RXEN 4
#define UDRIE 5
#define TXCIE 6
#define RXCIE 7
#define UCSRC _SFR_MEM8(0xC2)
#define UCPOL 0
#define UCSZ0 1
#define UCSZ1 2
#define USBS 3
#define UPM0 4
#define UPM1 5
#define UMSEL 6
/* Reserved [0xC3] */
/* Combine UBRRL and UBRRH */
#define UBRR _SFR_MEM16(0xC4)
#define UBRRL _SFR_MEM8(0xC4)
#define UBRRH _SFR_MEM8(0xC5)
#define UDR _SFR_MEM8(0XC6)
/* Reserved [0xC7..0xFF] */
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect_num 2
#define PCINT0_vect _VECTOR(2)
#define SIG_PIN_CHANGE0 _VECTOR(2)
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect_num 3
#define PCINT1_vect _VECTOR(3)
#define SIG_PIN_CHANGE1 _VECTOR(3)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 4
#define TIMER2_COMP_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 5
#define TIMER2_OVF_vect _VECTOR(5)
#define SIG_OVERFLOW2 _VECTOR(5)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 6
#define TIMER1_CAPT_vect _VECTOR(6)
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 7
#define TIMER1_COMPA_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect_num 8
#define TIMER1_COMPB_vect _VECTOR(8)
#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 9
#define TIMER1_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW1 _VECTOR(9)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 10
#define TIMER0_COMP_vect _VECTOR(10)
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 11
#define TIMER0_OVF_vect _VECTOR(11)
#define SIG_OVERFLOW0 _VECTOR(11)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 12
#define SPI_STC_vect _VECTOR(12)
#define SIG_SPI _VECTOR(12)
/* USART0, Rx Complete */
#define USART0_RX_vect_num 13
#define USART0_RX_vect _VECTOR(13)
#define USART_RX_vect _VECTOR(13) /* Alias */
#define SIG_UART_RECV _VECTOR(13)
/* USART0 Data register Empty */
#define USART0_UDRE_vect_num 14
#define USART0_UDRE_vect _VECTOR(14)
#define USART_UDRE_vect _VECTOR(14) /* Alias */
#define SIG_UART_DATA _VECTOR(14)
/* USART0, Tx Complete */
#define USART0_TX_vect_num 15
#define USART0_TX_vect _VECTOR(15)
#define USART_TX_vect _VECTOR(15) /* Alias */
#define SIG_UART_TRANS _VECTOR(15)
/* USI Start Condition */
#define USI_START_vect_num 16
#define USI_START_vect _VECTOR(16)
#define SIG_USI_START _VECTOR(16)
/* USI Overflow */
#define USI_OVERFLOW_vect_num 17
#define USI_OVERFLOW_vect _VECTOR(17)
#define SIG_USI_OVERFLOW _VECTOR(17)
/* Analog Comparator */
#define ANALOG_COMP_vect_num 18
#define ANALOG_COMP_vect _VECTOR(18)
#define SIG_COMPARATOR _VECTOR(18)
/* ADC Conversion Complete */
#define ADC_vect_num 19
#define ADC_vect _VECTOR(19)
#define SIG_ADC _VECTOR(19)
/* EEPROM Ready */
#define EE_READY_vect_num 20
#define EE_READY_vect _VECTOR(20)
#define SIG_EEPROM_READY _VECTOR(20)
/* Store Program Memory Read */
#define SPM_READY_vect_num 21
#define SPM_READY_vect _VECTOR(21)
#define SIG_SPM_READY _VECTOR(21)
#define _VECTORS_SIZE 88
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART 0x100
#define RAMEND 0x4FF
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x05
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_PIN_CHANGE0
#pragma GCC poison SIG_PIN_CHANGE1
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OUTPUT_COMPARE0
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison USART_RX_vect
#pragma GCC poison SIG_UART_RECV
#pragma GCC poison USART_UDRE_vect
#pragma GCC poison SIG_UART_DATA
#pragma GCC poison USART_TX_vect
#pragma GCC poison SIG_UART_TRANS
#pragma GCC poison SIG_USI_START
#pragma GCC poison SIG_USI_OVERFLOW
#pragma GCC poison SIG_COMPARATOR
#pragma GCC poison SIG_ADC
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_SPM_READY
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#endif /* _AVR_IOM165_H_ */

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/*****************************************************************************
*
* Copyright (C) 2014 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
/* $Id: iom165a.h 2442 2014-08-11 21:42:11Z joerg_wunsch $ */
#ifndef _AVR_ATMEGA165A_H_INCLUDED
#define _AVR_ATMEGA165A_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom165a.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDRA7 7
#define DDRA6 6
#define DDRA5 5
#define DDRA4 4
#define DDRA3 3
#define DDRA2 2
#define DDRA1 1
#define DDRA0 0
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
#define DDRB6 6
#define DDRB5 5
#define DDRB4 4
#define DDRB3 3
#define DDRB2 2
#define DDRB1 1
#define DDRB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC7 7
#define DDRC6 6
#define DDRC5 5
#define DDRC4 4
#define DDRC3 3
#define DDRC2 2
#define DDRC1 1
#define DDRC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
#define DDRD6 6
#define DDRD5 5
#define DDRD4 4
#define DDRD3 3
#define DDRD2 2
#define DDRD1 1
#define DDRD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDRE7 7
#define DDRE6 6
#define DDRE5 5
#define DDRE4 4
#define DDRE3 3
#define DDRE2 2
#define DDRE1 1
#define DDRE0 0
#define PORTE _SFR_IO8(0x0E)
#define PORTE7 7
#define PORTE6 6
#define PORTE5 5
#define PORTE4 4
#define PORTE3 3
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
#define PINF _SFR_IO8(0x0F)
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
#define DDRF _SFR_IO8(0x10)
#define DDRF7 7
#define DDRF6 6
#define DDRF5 5
#define DDRF4 4
#define DDRF3 3
#define DDRF2 2
#define DDRF1 1
#define DDRF0 0
#define PORTF _SFR_IO8(0x11)
#define PORTF7 7
#define PORTF6 6
#define PORTF5 5
#define PORTF4 4
#define PORTF3 3
#define PORTF2 2
#define PORTF1 1
#define PORTF0 0
#define PING _SFR_IO8(0x12)
#define PING5 5
#define PING4 4
#define PING3 3
#define PING2 2
#define PING1 1
#define PING0 0
#define DDRG _SFR_IO8(0x13)
#define DDRG4 4
#define DDRG3 3
#define DDRG2 2
#define DDRG1 1
#define DDRG0 0
#define PORTG _SFR_IO8(0x14)
#define PORTG4 4
#define PORTG3 3
#define PORTG2 2
#define PORTG1 1
#define PORTG0 0
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
/* Reserved [0x18..0x1B] */
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define PCIF0 4
#define PCIF1 5
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define PCIE0 4
#define PCIE1 5
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR310 0
#define TSM 7
#define PSR2 1
#define TCCR0A _SFR_IO8(0x24)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM0A0 4
#define COM0A1 5
#define WGM00 6
#define FOC0A 7
/* Reserved [0x25] */
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
/* Reserved [0x28..0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define OCDR _SFR_IO8(0x31)
#define OCDR7 7
#define OCDR6 6
#define OCDR5 5
#define OCDR4 4
#define OCDR3 3
#define OCDR2 2
#define OCDR1 1
#define OCDR0 0
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define JTRF 4
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define JTD 7
#define IVCE 0
#define IVSEL 1
#define PUD 4
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ACME 6
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM21 3
#define COM2A0 4
#define COM2A1 5
#define WGM20 6
#define FOC2A 7
/* Reserved [0xB1] */
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
/* Reserved [0xB4..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3
#define EXCLK 4
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
/* Reserved [0xBB..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL0 6
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(2)
#define PCINT0_vect_num 2
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(3)
#define PCINT1_vect_num 3
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect _VECTOR(4)
#define TIMER2_COMP_vect_num 4
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(5)
#define TIMER2_OVF_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect _VECTOR(10)
#define TIMER0_COMP_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(12)
#define SPI_STC_vect_num 12
/* USART0, Rx Complete */
#define USART0_RX_vect _VECTOR(13)
#define USART0_RX_vect_num 13
/* USART0 Data register Empty */
#define USART0_UDRE_vect _VECTOR(14)
#define USART0_UDRE_vect_num 14
/* USART0, Tx Complete */
#define USART0_TX_vect _VECTOR(15)
#define USART0_TX_vect_num 15
/* USI Start Condition */
#define USI_START_vect _VECTOR(16)
#define USI_START_vect_num 16
/* USI Overflow */
#define USI_OVERFLOW_vect _VECTOR(17)
#define USI_OVERFLOW_vect_num 17
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(18)
#define ANALOG_COMP_vect_num 18
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(19)
#define ADC_vect_num 19
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(20)
#define EE_READY_vect_num 20
/* Store Program Memory Read */
#define SPM_READY_vect _VECTOR(21)
#define SPM_READY_vect_num 21
#define _VECTORS_SIZE 88
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
/* Extended Fuse Byte */
#define FUSE_RSTDISBL (unsigned char)~_BV(0)
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x10
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* #ifdef _AVR_ATMEGA165A_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/iom165p.h
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@ -1,889 +0,0 @@
/* Copyright (c) 2004,2005,2006 Eric B. Weddington
Copyright (c) 2006 Anatoly Sokolov <aesok@post.ru>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */
/* avr/iom165p.h - definitions for ATmega165P */
#ifndef _AVR_IOM165P_H_
#define _AVR_IOM165P_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom165p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
#define PORTA _SFR_IO8(0x02)
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
#define PORTE _SFR_IO8(0x0E)
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
#define PINF _SFR_IO8(0x0F)
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
#define DDRF _SFR_IO8(0x10)
#define DDF7 7
#define DDF6 6
#define DDF5 5
#define DDF4 4
#define DDF3 3
#define DDF2 2
#define DDF1 1
#define DDF0 0
#define PORTF _SFR_IO8(0x11)
#define PF7 7
#define PF6 6
#define PF5 5
#define PF4 4
#define PF3 3
#define PF2 2
#define PF1 1
#define PF0 0
#define PING _SFR_IO8(0x12)
#define PING5 5
#define PING4 4
#define PING3 3
#define PING2 2
#define PING1 1
#define PING0 0
#define DDRG _SFR_IO8(0x13)
#define DDG4 4
#define DDG3 3
#define DDG2 2
#define DDG1 1
#define DDG0 0
#define PORTG _SFR_IO8(0x14)
#define PG4 4
#define PG3 3
#define PG2 2
#define PG1 1
#define PG0 0
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
/* Reserved [0x18..0x1B] */
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define PCIF0 6
#define PCIF1 7
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define PCIE0 6
#define PCIE1 7
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEDR _SFR_IO8(0X20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
#define __EEPROM_REG_LOCATIONS__ 1F2021
#define GTCCR _SFR_IO8(0x23)
#define PSR10 0
#define PSR2 1
#define TSM 7
#define TCCR0A _SFR_IO8(0x24)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM0A0 4
#define COM0A1 5
#define WGM00 6
#define FOC0A 7
/* Reserved [0x25] */
#define TCNT0 _SFR_IO8(0X26)
#define OCR0A _SFR_IO8(0X27)
/* Reserved [0x28..0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0X2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define OCDR _SFR_IO8(0x31)
#define OCDR0 0
#define OCDR1 1
#define OCDR2 2
#define OCDR3 3
#define OCDR4 4
#define OCDR5 5
#define OCDR6 6
#define OCD 7 // The datasheet defines this but IMO it should be OCDR7.
#define OCDR7 7
#define IDRD 7
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define JTRF 4
#define MCUCR _SFR_IO8(0X35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define JTD 7
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
/* Reserved [0x6A] */
/* Combine PCMSK0 and PCMSK1 */
#define PCMSK _SFR_MEM16(0x6B)
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0X80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0X81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM21 3
#define COM2A0 4
#define COM2A1 5
#define WGM20 6
#define FOC2A 7
/* Reserved [0xB1] */
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
/* Reserved [0xB4..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3
#define EXCLK 4
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
/* Reserved [0xBB..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0XC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL0 6
/* Reserved [0xC3] */
/* Combine UBRRL and UBRRH */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0XC6)
/* Reserved [0xC7..0xFF] */
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect_num 2
#define PCINT0_vect _VECTOR(2)
#define SIG_PIN_CHANGE0 _VECTOR(2)
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect_num 3
#define PCINT1_vect _VECTOR(3)
#define SIG_PIN_CHANGE1 _VECTOR(3)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 4
#define TIMER2_COMP_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 5
#define TIMER2_OVF_vect _VECTOR(5)
#define SIG_OVERFLOW2 _VECTOR(5)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 6
#define TIMER1_CAPT_vect _VECTOR(6)
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 7
#define TIMER1_COMPA_vect _VECTOR(7)
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect_num 8
#define TIMER1_COMPB_vect _VECTOR(8)
#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 9
#define TIMER1_OVF_vect _VECTOR(9)
#define SIG_OVERFLOW1 _VECTOR(9)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 10
#define TIMER0_COMP_vect _VECTOR(10)
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 11
#define TIMER0_OVF_vect _VECTOR(11)
#define SIG_OVERFLOW0 _VECTOR(11)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 12
#define SPI_STC_vect _VECTOR(12)
#define SIG_SPI _VECTOR(12)
/* USART0, Rx Complete */
#define USART0_RX_vect_num 13
#define USART0_RX_vect _VECTOR(13)
#define USART_RX_vect _VECTOR(13) /* Alias */
#define SIG_UART_RECV _VECTOR(13)
/* USART0 Data register Empty */
#define USART0_UDRE_vect_num 14
#define USART0_UDRE_vect _VECTOR(14)
#define USART_UDRE_vect _VECTOR(14) /* Alias */
#define SIG_UART_DATA _VECTOR(14)
/* USART0, Tx Complete */
#define USART0_TX_vect_num 15
#define USART0_TX_vect _VECTOR(15)
#define USART_TX_vect _VECTOR(15) /* Alias */
#define SIG_UART_TRANS _VECTOR(15)
/* USI Start Condition */
#define USI_START_vect_num 16
#define USI_START_vect _VECTOR(16)
#define SIG_USI_START _VECTOR(16)
/* USI Overflow */
#define USI_OVERFLOW_vect_num 17
#define USI_OVERFLOW_vect _VECTOR(17)
#define SIG_USI_OVERFLOW _VECTOR(17)
/* Analog Comparator */
#define ANALOG_COMP_vect_num 18
#define ANALOG_COMP_vect _VECTOR(18)
#define SIG_COMPARATOR _VECTOR(18)
/* ADC Conversion Complete */
#define ADC_vect_num 19
#define ADC_vect _VECTOR(19)
#define SIG_ADC _VECTOR(19)
/* EEPROM Ready */
#define EE_READY_vect_num 20
#define EE_READY_vect _VECTOR(20)
#define SIG_EEPROM_READY _VECTOR(20)
/* Store Program Memory Read */
#define SPM_READY_vect_num 21
#define SPM_READY_vect _VECTOR(21)
#define SIG_SPM_READY _VECTOR(21)
#define _VECTORS_SIZE 88
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART 0x100
#define RAMEND 0x4FF
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT0 (unsigned char)~_BV(4)
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x07
/* Deprecated items */
#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
#pragma GCC system_header
#pragma GCC poison SIG_INTERRUPT0
#pragma GCC poison SIG_PIN_CHANGE0
#pragma GCC poison SIG_PIN_CHANGE1
#pragma GCC poison SIG_OUTPUT_COMPARE2
#pragma GCC poison SIG_OVERFLOW2
#pragma GCC poison SIG_INPUT_CAPTURE1
#pragma GCC poison SIG_OUTPUT_COMPARE1A
#pragma GCC poison SIG_OUTPUT_COMPARE1B
#pragma GCC poison SIG_OVERFLOW1
#pragma GCC poison SIG_OUTPUT_COMPARE0
#pragma GCC poison SIG_OVERFLOW0
#pragma GCC poison SIG_SPI
#pragma GCC poison USART_RX_vect
#pragma GCC poison SIG_UART_RECV
#pragma GCC poison USART_UDRE_vect
#pragma GCC poison SIG_UART_DATA
#pragma GCC poison USART_TX_vect
#pragma GCC poison SIG_UART_TRANS
#pragma GCC poison SIG_USI_START
#pragma GCC poison SIG_USI_OVERFLOW
#pragma GCC poison SIG_COMPARATOR
#pragma GCC poison SIG_ADC
#pragma GCC poison SIG_EEPROM_READY
#pragma GCC poison SIG_SPM_READY
#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* _AVR_IOM165P_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom165pa.h
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@ -1,948 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATMEGA165PA_H_INCLUDED
#define _AVR_ATMEGA165PA_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom165pa.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
#define DDRA _SFR_IO8(0x01)
#define DDRA7 7
// Inserted "DDA7" from "DDRA7" due to compatibility
#define DDA7 7
#define DDRA6 6
// Inserted "DDA6" from "DDRA6" due to compatibility
#define DDA6 6
#define DDRA5 5
// Inserted "DDA5" from "DDRA5" due to compatibility
#define DDA5 5
#define DDRA4 4
// Inserted "DDA4" from "DDRA4" due to compatibility
#define DDA4 4
#define DDRA3 3
// Inserted "DDA3" from "DDRA3" due to compatibility
#define DDA3 3
#define DDRA2 2
// Inserted "DDA2" from "DDRA2" due to compatibility
#define DDA2 2
#define DDRA1 1
// Inserted "DDA1" from "DDRA1" due to compatibility
#define DDA1 1
#define DDRA0 0
// Inserted "DDA0" from "DDRA0" due to compatibility
#define DDA0 0
#define PORTA _SFR_IO8(0x02)
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC7 7
// Inserted "DDC7" from "DDRC7" due to compatibility
#define DDC7 7
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDRE7 7
// Inserted "DDE7" from "DDRE7" due to compatibility
#define DDE7 7
#define DDRE6 6
// Inserted "DDE6" from "DDRE6" due to compatibility
#define DDE6 6
#define DDRE5 5
// Inserted "DDE5" from "DDRE5" due to compatibility
#define DDE5 5
#define DDRE4 4
// Inserted "DDE4" from "DDRE4" due to compatibility
#define DDE4 4
#define DDRE3 3
// Inserted "DDE3" from "DDRE3" due to compatibility
#define DDE3 3
#define DDRE2 2
// Inserted "DDE2" from "DDRE2" due to compatibility
#define DDE2 2
#define DDRE1 1
// Inserted "DDE1" from "DDRE1" due to compatibility
#define DDE1 1
#define DDRE0 0
// Inserted "DDE0" from "DDRE0" due to compatibility
#define DDE0 0
#define PORTE _SFR_IO8(0x0E)
#define PORTE7 7
#define PORTE6 6
#define PORTE5 5
#define PORTE4 4
#define PORTE3 3
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
#define PINF _SFR_IO8(0x0F)
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
#define DDRF _SFR_IO8(0x10)
#define DDRF7 7
// Inserted "DDF7" from "DDRF7" due to compatibility
#define DDF7 7
#define DDRF6 6
// Inserted "DDF6" from "DDRF6" due to compatibility
#define DDF6 6
#define DDRF5 5
// Inserted "DDF5" from "DDRF5" due to compatibility
#define DDF5 5
#define DDRF4 4
// Inserted "DDF4" from "DDRF4" due to compatibility
#define DDF4 4
#define DDRF3 3
// Inserted "DDF3" from "DDRF3" due to compatibility
#define DDF3 3
#define DDRF2 2
// Inserted "DDF2" from "DDRF2" due to compatibility
#define DDF2 2
#define DDRF1 1
// Inserted "DDF1" from "DDRF1" due to compatibility
#define DDF1 1
#define DDRF0 0
// Inserted "DDF0" from "DDRF0" due to compatibility
#define DDF0 0
#define PORTF _SFR_IO8(0x11)
#define PORTF7 7
#define PORTF6 6
#define PORTF5 5
#define PORTF4 4
#define PORTF3 3
#define PORTF2 2
#define PORTF1 1
#define PORTF0 0
#define PING _SFR_IO8(0x12)
#define PING5 5
#define PING4 4
#define PING3 3
#define PING2 2
#define PING1 1
#define PING0 0
#define DDRG _SFR_IO8(0x13)
#define DDRG4 4
// Inserted "DDG4" from "DDRG4" due to compatibility
#define DDG4 4
#define DDRG3 3
// Inserted "DDG3" from "DDRG3" due to compatibility
#define DDG3 3
#define DDRG2 2
// Inserted "DDG2" from "DDRG2" due to compatibility
#define DDG2 2
#define DDRG1 1
// Inserted "DDG1" from "DDRG1" due to compatibility
#define DDG1 1
#define DDRG0 0
// Inserted "DDG0" from "DDRG0" due to compatibility
#define DDG0 0
#define PORTG _SFR_IO8(0x14)
#define PORTG4 4
#define PORTG3 3
#define PORTG2 2
#define PORTG1 1
#define PORTG0 0
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
/* Reserved [0x18..0x1B] */
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define PCIF0 4
#define PCIF1 5
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define PCIE0 4
#define PCIE1 5
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEWE 1
#define EEMWE 2
#define EERIE 3
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSR310 0
#define TSM 7
#define PSR2 1
#define TCCR0A _SFR_IO8(0x24)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM01 3
#define COM0A0 4
#define COM0A1 5
#define WGM00 6
#define FOC0A 7
/* Reserved [0x25] */
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
/* Reserved [0x28..0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define OCDR _SFR_IO8(0x31)
#define OCDR7 7
#define OCDR6 6
#define OCDR5 5
#define OCDR4 4
#define OCDR3 3
#define OCDR2 2
#define OCDR1 1
#define OCDR0 0
/* Reserved [0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define JTRF 4
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define JTD 7
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67..0x68] */
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCINT15 7
/* Reserved [0x6D] */
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ACME 6
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define MUX4 4
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM21 3
#define COM2A0 4
#define COM2A1 5
#define WGM20 6
#define FOC2A 7
/* Reserved [0xB1] */
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
/* Reserved [0xB4..0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2UB 0
#define OCR2UB 1
#define TCN2UB 2
#define AS2 3
#define EXCLK 4
/* Reserved [0xB7] */
#define USICR _SFR_MEM8(0xB8)
#define USITC 0
#define USICLK 1
#define USICS0 2
#define USICS1 3
#define USIWM0 4
#define USIWM1 5
#define USIOIE 6
#define USISIE 7
#define USISR _SFR_MEM8(0xB9)
#define USICNT0 0
#define USICNT1 1
#define USICNT2 2
#define USICNT3 3
#define USIDC 4
#define USIPF 5
#define USIOIF 6
#define USISIF 7
#define USIDR _SFR_MEM8(0xBA)
/* Reserved [0xBB..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL0 6
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(2)
#define PCINT0_vect_num 2
/* Pin Change Interrupt Request 1 */
#define PCINT1_vect _VECTOR(3)
#define PCINT1_vect_num 3
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect _VECTOR(4)
#define TIMER2_COMP_vect_num 4
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(5)
#define TIMER2_OVF_vect_num 5
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(6)
#define TIMER1_CAPT_vect_num 6
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(7)
#define TIMER1_COMPA_vect_num 7
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(8)
#define TIMER1_COMPB_vect_num 8
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(9)
#define TIMER1_OVF_vect_num 9
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect _VECTOR(10)
#define TIMER0_COMP_vect_num 10
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(11)
#define TIMER0_OVF_vect_num 11
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(12)
#define SPI_STC_vect_num 12
/* USART0, Rx Complete */
#define USART0_RX_vect _VECTOR(13)
#define USART0_RX_vect_num 13
/* USART0 Data register Empty */
#define USART0_UDRE_vect _VECTOR(14)
#define USART0_UDRE_vect_num 14
/* USART0, Tx Complete */
#define USART0_TX_vect _VECTOR(15)
#define USART0_TX_vect_num 15
/* USI Start Condition */
#define USI_START_vect _VECTOR(16)
#define USI_START_vect_num 16
/* USI Overflow */
#define USI_OVERFLOW_vect _VECTOR(17)
#define USI_OVERFLOW_vect_num 17
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(18)
#define ANALOG_COMP_vect_num 18
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(19)
#define ADC_vect_num 19
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(20)
#define EE_READY_vect_num 20
/* Store Program Memory Read */
#define SPM_READY_vect _VECTOR(21)
#define SPM_READY_vect_num 21
#define _VECTORS_SIZE 88
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_RSTDISBL (unsigned char)~_BV(0)
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (0xFF)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x07
#endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */

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/* Copyright (c) 2004, Theodore A. Roth
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom168.h 2115 2010-04-05 23:19:53Z arcanum $ */
#ifndef _AVR_IOM168_H_
#define _AVR_IOM168_H_ 1
#include <avr/iomx8.h>
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART (0x100)
#define RAMEND 0x4FF
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x06
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#endif /* _AVR_IOM168_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom168a.h
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/*****************************************************************************
*
* Copyright (C) 2011 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#include "iom168.h"
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)

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arduino/hardware/tools/avr/avr/include/avr/iom168p.h
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/* Copyright (c) 2007 Atmel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */
/* avr/iom168p.h - definitions for ATmega168P. */
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom168p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#ifndef _AVR_IOM168P_H_
#define _AVR_IOM168P_H_ 1
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
#define PINC _SFR_IO8(0x06)
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define DDRC _SFR_IO8(0x07)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define PORTC _SFR_IO8(0x08)
#define PORTC0 0
#define PORTC1 1
#define PORTC2 2
#define PORTC3 3
#define PORTC4 4
#define PORTC5 5
#define PORTC6 6
#define PIND _SFR_IO8(0x09)
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7
#define EEARH _SFR_IO8(0x22)
#define EEAR8 0
#define EEPROM_REG_LOCATIONS 1F2021
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define PSRASY 1
#define TSM 7
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7
#define OCR0A _SFR_IO8(0x27)
#define OCR0A_0 0
#define OCR0A_1 1
#define OCR0A_2 2
#define OCR0A_3 3
#define OCR0A_4 4
#define OCR0A_5 5
#define OCR0A_6 6
#define OCR0A_7 7
#define OCR0B _SFR_IO8(0x28)
#define OCR0B_0 0
#define OCR0B_1 1
#define OCR0B_2 2
#define OCR0B_3 3
#define OCR0B_4 4
#define OCR0B_5 5
#define OCR0B_6 6
#define OCR0B_7 7
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
#define SPDR0 0
#define SPDR1 1
#define SPDR2 2
#define SPDR3 3
#define SPDR4 4
#define SPDR5 5
#define SPDR6 6
#define SPDR7 7
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
#define WDTCSR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
#define OSCCAL _SFR_MEM8(0x66)
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7
#define ADCH _SFR_MEM8(0x79)
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7
#define TCNT1H _SFR_MEM8(0x85)
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7
#define ICR1H _SFR_MEM8(0x87)
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7
#define OCR1AH _SFR_MEM8(0x89)
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BL0 0
#define OCR1BL1 1
#define OCR1BL2 2
#define OCR1BL3 3
#define OCR1BL4 4
#define OCR1BL5 5
#define OCR1BL6 6
#define OCR1BL7 7
#define OCR1BH _SFR_MEM8(0x8B)
#define OCR1BH0 0
#define OCR1BH1 1
#define OCR1BH2 2
#define OCR1BH3 3
#define OCR1BH4 4
#define OCR1BH5 5
#define OCR1BH6 6
#define OCR1BH7 7
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define TCNT2_0 0
#define TCNT2_1 1
#define TCNT2_2 2
#define TCNT2_3 3
#define TCNT2_4 4
#define TCNT2_5 5
#define TCNT2_6 6
#define TCNT2_7 7
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7
#define OCR2B _SFR_MEM8(0xB4)
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
#define TWBR _SFR_MEM8(0xB8)
#define TWBR0 0
#define TWBR1 1
#define TWBR2 2
#define TWBR3 3
#define TWBR4 4
#define TWBR5 5
#define TWBR6 6
#define TWBR7 7
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWD0 0
#define TWD1 1
#define TWD2 2
#define TWD3 3
#define TWD4 4
#define TWD5 5
#define TWD6 6
#define TWD7 7
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 0
#define TWAM1 1
#define TWAM2 2
#define TWAM3 3
#define TWAM4 4
#define TWAM5 5
#define TWAM6 6
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCPHA0 1
#define UCSZ01 2
#define UDORD0 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0_0 0
#define UBRR0_1 1
#define UBRR0_2 2
#define UBRR0_3 3
#define UBRR0_4 4
#define UBRR0_5 5
#define UBRR0_6 6
#define UBRR0_7 7
#define UBRR0H _SFR_MEM8(0xC5)
#define UBRR0_8 0
#define UBRR0_9 1
#define UBRR0_10 2
#define UBRR0_11 3
#define UDR0 _SFR_MEM8(0xC6)
#define UDR0_0 0
#define UDR0_1 1
#define UDR0_2 2
#define UDR0_3 3
#define UDR0_4 4
#define UDR0_5 5
#define UDR0_6 6
#define UDR0_7 7
/* Interrupt Vectors */
/* Interrupt Vector 0 is the reset vector. */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
#define PCINT0_vect_num 3
#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
#define PCINT1_vect_num 4
#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
#define PCINT2_vect_num 5
#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
#define WDT_vect_num 6
#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
#define TIMER2_COMPA_vect_num 7
#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect_num 8
#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
#define TIMER2_OVF_vect_num 9
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect_num 10
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect_num 11
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
#define TIMER1_COMPB_vect_num 12
#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect_num 13
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect_num 14
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect_num 15
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
#define TIMER0_OVF_vect_num 16
#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
#define SPI_STC_vect_num 17
#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
#define USART_RX_vect_num 18
#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
#define USART_UDRE_vect_num 19
#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
#define USART_TX_vect_num 20
#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
#define ADC_vect_num 21
#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
#define EE_READY_vect_num 22
#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
#define ANALOG_COMP_vect_num 23
#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
#define TWI_vect_num 24
#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
#define SPM_READY_vect_num 25
#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
#define _VECTORS_SIZE (26 * 4)
/* Constants */
#define SPM_PAGESIZE 128
#define RAMSTART (0x100)
#define RAMEND 0x4FF /* Last On-Chip SRAM Location */
#define XRAMSIZE 0
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x0B
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
#endif /* _AVR_IOM168P_H_ */

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arduino/hardware/tools/avr/avr/include/avr/iom168pa.h
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/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATMEGA168PA_H_INCLUDED
#define _AVR_ATMEGA168PA_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom168pa.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Reserved [0x0C..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
/* Reserved [0x18..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define TSM 7
#define PSRASY 1
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
#define OCR0B _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
/* Reserved [0x31..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCSR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2B _SFR_MEM8(0xB4)
/* Reserved [0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
/* Reserved [0xB7] */
#define TWBR _SFR_MEM8(0xB8)
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
/* Reserved [0xBE..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
/* Reserved [0xC3] */
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 1 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Watchdog Time-out Interrupt */
#define WDT_vect _VECTOR(6)
#define WDT_vect_num 6
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect _VECTOR(7)
#define TIMER2_COMPA_vect_num 7
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8)
#define TIMER2_COMPB_vect_num 8
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(9)
#define TIMER2_OVF_vect_num 9
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(10)
#define TIMER1_CAPT_vect_num 10
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(11)
#define TIMER1_COMPA_vect_num 11
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 12
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 13
/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(14)
#define TIMER0_COMPA_vect_num 14
/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 15
/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SPI_STC_vect_num 17
/* USART Rx Complete */
#define USART_RX_vect _VECTOR(18)
#define USART_RX_vect_num 18
/* USART, Data Register Empty */
#define USART_UDRE_vect _VECTOR(19)
#define USART_UDRE_vect_num 19
/* USART Tx Complete */
#define USART_TX_vect _VECTOR(20)
#define USART_TX_vect_num 20
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define ADC_vect_num 21
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define EE_READY_vect_num 22
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define ANALOG_COMP_vect_num 23
/* Two-wire Serial Interface */
#define TWI_vect _VECTOR(24)
#define TWI_vect_num 24
/* Store Program Memory Read */
#define SPM_Ready_vect _VECTOR(25)
#define SPM_Ready_vect_num 25
#define _VECTORS_SIZE 104
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x0B
#endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/iom168pb.h
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@ -1,899 +0,0 @@
/*****************************************************************************
*
* Copyright (C) 2015 Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
****************************************************************************/
#ifndef _AVR_ATMEGA168PB_H_INCLUDED
#define _AVR_ATMEGA168PB_H_INCLUDED
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom168pb.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
#define DDRB _SFR_IO8(0x04)
#define DDRB7 7
// Inserted "DDB7" from "DDRB7" due to compatibility
#define DDB7 7
#define DDRB6 6
// Inserted "DDB6" from "DDRB6" due to compatibility
#define DDB6 6
#define DDRB5 5
// Inserted "DDB5" from "DDRB5" due to compatibility
#define DDB5 5
#define DDRB4 4
// Inserted "DDB4" from "DDRB4" due to compatibility
#define DDB4 4
#define DDRB3 3
// Inserted "DDB3" from "DDRB3" due to compatibility
#define DDB3 3
#define DDRB2 2
// Inserted "DDB2" from "DDRB2" due to compatibility
#define DDB2 2
#define DDRB1 1
// Inserted "DDB1" from "DDRB1" due to compatibility
#define DDB1 1
#define DDRB0 0
// Inserted "DDB0" from "DDRB0" due to compatibility
#define DDB0 0
#define PORTB _SFR_IO8(0x05)
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
#define PINC _SFR_IO8(0x06)
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
#define DDRC _SFR_IO8(0x07)
#define DDRC6 6
// Inserted "DDC6" from "DDRC6" due to compatibility
#define DDC6 6
#define DDRC5 5
// Inserted "DDC5" from "DDRC5" due to compatibility
#define DDC5 5
#define DDRC4 4
// Inserted "DDC4" from "DDRC4" due to compatibility
#define DDC4 4
#define DDRC3 3
// Inserted "DDC3" from "DDRC3" due to compatibility
#define DDC3 3
#define DDRC2 2
// Inserted "DDC2" from "DDRC2" due to compatibility
#define DDC2 2
#define DDRC1 1
// Inserted "DDC1" from "DDRC1" due to compatibility
#define DDC1 1
#define DDRC0 0
// Inserted "DDC0" from "DDRC0" due to compatibility
#define DDC0 0
#define PORTC _SFR_IO8(0x08)
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
#define PIND _SFR_IO8(0x09)
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
#define DDRD _SFR_IO8(0x0A)
#define DDRD7 7
// Inserted "DDD7" from "DDRD7" due to compatibility
#define DDD7 7
#define DDRD6 6
// Inserted "DDD6" from "DDRD6" due to compatibility
#define DDD6 6
#define DDRD5 5
// Inserted "DDD5" from "DDRD5" due to compatibility
#define DDD5 5
#define DDRD4 4
// Inserted "DDD4" from "DDRD4" due to compatibility
#define DDD4 4
#define DDRD3 3
// Inserted "DDD3" from "DDRD3" due to compatibility
#define DDD3 3
#define DDRD2 2
// Inserted "DDD2" from "DDRD2" due to compatibility
#define DDD2 2
#define DDRD1 1
// Inserted "DDD1" from "DDRD1" due to compatibility
#define DDD1 1
#define DDRD0 0
// Inserted "DDD0" from "DDRD0" due to compatibility
#define DDD0 0
#define PORTD _SFR_IO8(0x0B)
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
#define PINE _SFR_IO8(0x0C)
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
#define DDRE _SFR_IO8(0x0D)
#define DDRE3 3
// Inserted "DDE3" from "DDRE3" due to compatibility
#define DDE3 3
#define DDRE2 2
// Inserted "DDE2" from "DDRE2" due to compatibility
#define DDE2 2
#define DDRE1 1
// Inserted "DDE1" from "DDRE1" due to compatibility
#define DDE1 1
#define DDRE0 0
// Inserted "DDE0" from "DDRE0" due to compatibility
#define DDE0 0
#define PORTE _SFR_IO8(0x0E)
#define PORTE3 3
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
#define ACSRB _SFR_IO8(0x0F)
#define ACOE 0
/* Reserved [0x10..0x14] */
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
/* Reserved [0x18..0x1A] */
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
/* Combine EEARL and EEARH */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define TSM 7
#define PSRASY 1
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define OCR0A _SFR_IO8(0x27)
#define OCR0B _SFR_IO8(0x28)
/* Reserved [0x29] */
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR2 _SFR_IO8(0x2B)
#define SPCR _SFR_IO8(0x2C)
#define SPR0 0
#define SPR1 1
#define CPHA 2
#define CPOL 3
#define MSTR 4
#define DORD 5
#define SPE 6
#define SPIE 7
#define SPSR _SFR_IO8(0x2D)
#define SPI2X 0
#define WCOL 6
#define SPIF 7
#define SPDR _SFR_IO8(0x2E)
/* Reserved [0x2F] */
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
/* Reserved [0x31..0x32] */
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
/* Reserved [0x36] */
#define SPMCSR _SFR_IO8(0x37)
#define SPMEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define SIGRD 5
#define RWWSB 6
#define SPMIE 7
/* Reserved [0x38..0x3C] */
/* SP [0x3D..0x3E] */
/* SREG [0x3F] */
#define WDTCSR _SFR_MEM8(0x60)
#define WDE 3
#define WDCE 4
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
/* Reserved [0x62..0x63] */
#define PRR _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI 2
#define PRTIM1 3
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI 7
#define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
#define __AVR_HAVE_PRR_PRADC
#define __AVR_HAVE_PRR_PRUSART0
#define __AVR_HAVE_PRR_PRSPI
#define __AVR_HAVE_PRR_PRTIM1
#define __AVR_HAVE_PRR_PRTIM0
#define __AVR_HAVE_PRR_PRTIM2
#define __AVR_HAVE_PRR_PRTWI
/* Reserved [0x65] */
#define OSCCAL _SFR_MEM8(0x66)
#define OSCCAL0 0
#define OSCCAL1 1
#define OSCCAL2 2
#define OSCCAL3 3
#define OSCCAL4 4
#define OSCCAL5 5
#define OSCCAL6 6
#define OSCCAL7 7
/* Reserved [0x67] */
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
/* Reserved [0x6A] */
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
/* Reserved [0x71..0x77] */
/* Combine ADCL and ADCH */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
/* Reserved [0x7D] */
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
/* Reserved [0x83] */
/* Combine TCNT1L and TCNT1H */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* Combine ICR1L and ICR1H */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* Combine OCR1AL and OCR1AH */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* Combine OCR1BL and OCR1BH */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* Reserved [0x8C..0xAF] */
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2B _SFR_MEM8(0xB4)
/* Reserved [0xB5] */
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
/* Reserved [0xB7] */
#define TWBR _SFR_MEM8(0xB8)
#define TWSR _SFR_MEM8(0xB9)
#define TWPS0 0
#define TWPS1 1
#define TWS3 3
#define TWS4 4
#define TWS5 5
#define TWS6 6
#define TWS7 7
#define TWAR _SFR_MEM8(0xBA)
#define TWGCE 0
#define TWA0 1
#define TWA1 2
#define TWA2 3
#define TWA3 4
#define TWA4 5
#define TWA5 6
#define TWA6 7
#define TWDR _SFR_MEM8(0xBB)
#define TWCR _SFR_MEM8(0xBC)
#define TWIE 0
#define TWEN 2
#define TWWC 3
#define TWSTO 4
#define TWSTA 5
#define TWEA 6
#define TWINT 7
#define TWAMR _SFR_MEM8(0xBD)
#define TWAM0 1
#define TWAM1 2
#define TWAM2 3
#define TWAM3 4
#define TWAM4 5
#define TWAM5 6
#define TWAM6 7
/* Reserved [0xBE..0xBF] */
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCSZ01 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
#define UCSR0D _SFR_MEM8(0xC3)
#define SFDE 5
#define RXS 6
#define RXSIE 7
/* Combine UBRR0L and UBRR0H */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
#define UDR0 _SFR_MEM8(0xC6)
/* Reserved [0xC7..0xEF] */
#define DEVID0 _SFR_MEM8(0xF0)
#define DEVID1 _SFR_MEM8(0xF1)
#define DEVID2 _SFR_MEM8(0xF2)
#define DEVID3 _SFR_MEM8(0xF3)
#define DEVID4 _SFR_MEM8(0xF4)
#define DEVID5 _SFR_MEM8(0xF5)
#define DEVID6 _SFR_MEM8(0xF6)
#define DEVID7 _SFR_MEM8(0xF7)
#define DEVID8 _SFR_MEM8(0xF8)
/* Values and associated defines */
#define SLEEP_MODE_IDLE (0x00<<1)
#define SLEEP_MODE_ADC (0x01<<1)
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
#define SLEEP_MODE_STANDBY (0x06<<1)
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
/* Interrupt vectors */
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define INT0_vect_num 1
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define INT1_vect_num 2
/* Pin Change Interrupt Request 0 */
#define PCINT0_vect _VECTOR(3)
#define PCINT0_vect_num 3
/* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4)
#define PCINT1_vect_num 4
/* Pin Change Interrupt Request 1 */
#define PCINT2_vect _VECTOR(5)
#define PCINT2_vect_num 5
/* Watchdog Time-out Interrupt */
#define WDT_vect _VECTOR(6)
#define WDT_vect_num 6
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect _VECTOR(7)
#define TIMER2_COMPA_vect_num 7
/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8)
#define TIMER2_COMPB_vect_num 8
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(9)
#define TIMER2_OVF_vect_num 9
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(10)
#define TIMER1_CAPT_vect_num 10
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(11)
#define TIMER1_COMPA_vect_num 11
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 12
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 13
/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(14)
#define TIMER0_COMPA_vect_num 14
/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 15
/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 16
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SPI_STC_vect_num 17
/* USART Rx Complete */
#define USART_RX_vect _VECTOR(18)
#define USART_RX_vect_num 18
/* USART, Data Register Empty */
#define USART_UDRE_vect _VECTOR(19)
#define USART_UDRE_vect_num 19
/* USART Tx Complete */
#define USART_TX_vect _VECTOR(20)
#define USART_TX_vect_num 20
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define ADC_vect_num 21
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define EE_READY_vect_num 22
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define ANALOG_COMP_vect_num 23
/* Two-wire Serial Interface */
#define TWI_vect _VECTOR(24)
#define TWI_vect_num 24
/* Store Program Memory Read */
#define SPM_Ready_vect _VECTOR(25)
#define SPM_Ready_vect_num 25
/* USART Start Edge Interrupt */
#define USART_START_vect _VECTOR(26)
#define USART_START_vect_num 26
#define _VECTORS_SIZE 108
/* Constants */
#define SPM_PAGESIZE 128
#define FLASHSTART 0x0000
#define FLASHEND 0x3FFF
#define RAMSTART 0x0100
#define RAMSIZE 1024
#define RAMEND 0x04FF
#define E2START 0
#define E2SIZE 512
#define E2PAGESIZE 4
#define E2END 0x01FF
#define XRAMEND RAMEND
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4)
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x15
#endif /* #ifdef _AVR_ATMEGA168PB_H_INCLUDED */

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arduino/hardware/tools/avr/avr/include/avr/iom169.h
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